Shared PLL Architecture With Selective VCOs for Multi-Frequency Clocks

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Solution Overview

Problem

Conventional wireless distribution systems (WDS) require multiple phase locked loops (PLLs) to support different clock frequencies, leading to increased costs and space consumption due to duplicative solutions, especially in power-saving and space-constrained environments.

Innovation Solution

A single PLL with two voltage-controlled oscillators (VCOs) is used, where only one VCO is active at a time, sharing a phase detector and loop filter to generate feedback signals for different frequencies, reducing component count and space requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple PLLs are used to support different clock frequencies, then frequency support capability is improved, but device complexity and space consumption increase

Engineering Contradiction:

Improvefrequency support capabilityVSAvoiddevice complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent combines multiple PLL circuits into a single shared PLL infrastructure. Multiple VCOs are integrated within one PLL block, sharing common phase detectors, loop filters, and control logic. This merging approach maintains the ability to support multiple clock frequencies while significantly reducing the overall device complexity and component count compared to using separate PLL circuits for each frequency.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent creates a universal PLL structure that can perform multiple frequency synthesis functions through a single circuit block. The shared PLL infrastructure with multiple VCOs can be dynamically configured to generate different clock frequencies as needed, making the circuit multi-functional and adaptable to various frequency requirements without requiring dedicated PLL circuits for each function.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If multiple PLLs are used to support different clock frequencies, then frequency support capability is improved, but space consumption increases

Engineering Contradiction:

Improvefrequency support capabilityVSAvoidspace consumption

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent merges multiple PLL circuits into a single integrated structure where multiple VCOs share common phase detectors, loop filters, and control mechanisms. This consolidation dramatically reduces the physical space required on the integrated circuit compared to implementing separate PLL circuits for each frequency, while maintaining full frequency support capability.

Inventive Principle:

Principle #5Merging (Combining)

3Adaptability or versatility

If multiple PLLs are used to support different clock frequencies, then frequency support capability is improved, but cost increases

Engineering Contradiction:

Improvefrequency support capabilityVSAvoidcost

Core Design Contradiction:

Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent consolidates multiple PLL circuits into a single shared infrastructure with multiple VCOs, reducing the total component count and manufacturing complexity. This merging approach lowers production costs while maintaining the ability to support multiple clock frequencies through dynamic configuration of the shared resources.

Inventive Principle:

Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This consolidation of PLLs into a single unit with selectively enabled VCOs results in cost savings and reduced space usage while maintaining effective frequency support, enhancing overall system performance.

Implementation Method 1

a phase detector. The phase detector is configured to receive a reference input signal and one of two feedback signals. The phase detector is also configured to output a control signal

Methodology Applied

Scientific EffectPhase detection:

Implementation Method 2

a first voltage-controlled oscillator (VCO). The first VCO is configured to receive the control signal and output a first one of the two feedback signals... a second voltage-controlled oscillator (VCO). The second VCO is configured to receive the control signal and output a second one of the two feedback signals

Methodology Applied

Scientific EffectVoltage-controlled oscillation:

Data Source

PatentUS10389372B1Systems and methods for using a phase locked loop (PLL) to provide multiple output signals

Publication Date: 2019.08.20 ANI ACQUISITION SUB LLC

AI summary

A phase locked loop (PLL) provides output signals at multiple frequencies. In particular, the PLL includes a phase detector and two voltage controlled oscillators (VCOs). One of the VCOs is selectively enabled depending on a desired output signal. The phase detector receives a reference signal and a feedback signal from the enabled one of the two VCOs. The phase detector outputs a control signal that controls the VCO that provided the feedback signal.