Semiconductor Memory Cell Regions With Shared Row Decoder Layout
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently propagating voltage to word lines due to high wiring resistance, which degrades write and read performance, especially with the miniaturization and increased density of memory cell transistors.
Innovation Solution
Incorporating a connection region between cell regions that short-circuits select gate lines and word lines, allowing for simultaneous voltage application to both cell regions, thereby reducing wiring length and resistance, and sharing the row decoder module to improve voltage propagation speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell transistors are miniaturized and density is increased, then storage capacity is improved, but wiring resistance increases and voltage propagation speed decreases
Solution Approach 1:
The memory cell array is divided into multiple cell regions (first cell region and second cell region) with connection regions positioned between them. This segmentation allows for localized voltage application and reduces the overall wiring length required to reach all memory cells, thereby maintaining voltage propagation performance despite increased density.
Solution Approach 2:
Connection regions are positioned between cell regions in a spatial arrangement that short-circuits select gate lines and word lines. This three-dimensional positioning reduces wiring length and resistance by creating direct electrical pathways, improving voltage propagation speed without sacrificing memory cell density.
2Speed
If wiring length is reduced to improve voltage propagation, then area for row decoder module increases
Solution Approach 1:
The row decoder module is shared between the first and second cell regions, allowing a single decoder to control word lines in both regions. This merging eliminates the need for separate decoders, reducing the overall area required while maintaining fast voltage propagation through the connection regions.
Solution Approach 2:
The connection region serves multiple functions: it short-circuits select gate lines and word lines, provides electrical pathways for voltage propagation, and enables the shared row decoder to control both cell regions. This multi-functionality reduces the need for additional dedicated structures, minimizing area overhead.
3Reliability
If select gate lines and word lines are short-circuited in connection regions, then wiring resistance is reduced, but device complexity increases
Solution Approach 1:
The connection regions utilize the existing select gate lines and word lines to create short-circuit pathways, rather than requiring entirely new wiring structures. The existing conductive elements serve dual purposes: their original function and creating reduced-resistance pathways, thereby reducing wiring resistance without significantly increasing device complexity.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a first cell region including a plurality of memory cells, a second cell region including a plurality of memory cells, a connection region between the first cell region and the second cell region, and a row decoder for propagating a voltage to word lines in the first and second cell regions via the connection region.