Shared Row Address Refresh Layout for Multi-Bank Memory
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Solution Overview
Problem
Existing memory devices face challenges in reducing size and power consumption due to the separate arrangement of memory cell arrays and the need for individual refresh operations in each bank, which increases complexity and resource utilization.
Innovation Solution
A memory device design that merges decoded row address drivers and shares a single row address signal between two banks, allowing simultaneous per-bank refresh operations and reducing the area and current consumption by half.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate decoded row address drivers are provided for each bank, then each bank can independently perform refresh operations, but the device size and power consumption increase
Solution Approach 1:
The patent merges the decoded row address drivers of two banks into a single shared driver. The single decoded row address signal is simultaneously provided to both banks, enabling them to perform refresh operations independently while sharing the same driver circuitry. This reduces the overall device area while maintaining the capability for independent bank operations.
Solution Approach 2:
The single decoded row address driver is designed to serve multiple banks simultaneously. It can provide decoded row address signals to any combination of banks, enabling universal operation across different bank configurations. This multi-functional driver replaces multiple dedicated drivers, reducing device size while preserving operational flexibility.
2Reliability
If separate decoded row address drivers are provided for each bank, then each bank can independently perform refresh operations, but the power consumption increases
Solution Approach 1:
The patent merges the decoded row address drivers of two banks into a single shared driver. The single decoded row address signal is simultaneously provided to both banks, enabling them to perform refresh operations independently while sharing the same driver circuitry. This reduces the overall device area while maintaining the capability for independent bank operations.
Solution Approach 2:
The single decoded row address driver is designed to serve multiple banks simultaneously. It can provide decoded row address signals to any combination of banks, enabling universal operation across different bank configurations. This multi-functional driver replaces multiple dedicated drivers, reducing device size while preserving operational flexibility.
3Reliability
If individual refresh operations are performed in each bank, then data integrity is maintained, but the complexity and resource utilization increase
Solution Approach 1:
The patent merges the decoded row address drivers of two banks into a single shared driver. The single decoded row address signal is simultaneously provided to both banks, enabling them to perform refresh operations independently while sharing the same driver circuitry. This reduces the overall device area while maintaining the capability for independent bank operations.
Data Source
AI summary
A memory device includes plural banks that perform a per-bank refresh (PBR) operation, and an address register that provides a single row address signal to two banks of the plural banks, the two banks simultaneously performing the PBR operation and the single row address signal being shared by the two banks. The two banks activate a word line of each memory cell array based on a single decoded row address signal that is generated based on the single row address signal.