Integrated Circuit Package With Shared Scan Chains for Multi-Chip Testing
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Solution Overview
Problem
Existing methods for testing semiconductor chips in multi-chip packages are limited by the physical constraints of exposing all test pads, making it difficult to connect a test device to defective chips, necessitating separate inspection.
Innovation Solution
An integrated circuit package with two test circuits sharing a scan chain, utilizing a signal selection circuit to determine which test circuit to use based on a selection signal, allowing for both electric die sorting (EDS) and package testing without separate chip inspection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If all test pads are exposed to the outside in a multi-chip package, then each chip can be inspected separately for defects, but it is physically limited and requires separate inspection for each chip
Solution Approach 1:
The patent combines multiple test circuits (first test circuit and second test circuit) to share a common scan chain, allowing simultaneous testing of multiple chips through a single test pad interface. This merging approach enables defect detection for multiple chips without requiring separate exposed test pads for each chip, thus reducing package structure complexity while maintaining measurement precision.
Solution Approach 2:
The scan chain is designed to serve multiple functions: it can be used by both the first test circuit and the second test circuit for testing different chips. The signal selection circuit enables the same physical infrastructure to be universally applied for different testing scenarios, eliminating the need for separate dedicated test pads for each chip.
2Area of stationary object
If a single scan chain is shared by multiple test circuits, then spatial efficiency is improved and fewer test pads are needed, but signal routing and selection complexity increases
Solution Approach 1:
The signal selection circuit acts as an intermediary component that manages the sharing of the scan chain between multiple test circuits. It receives control signals and selectively connects the appropriate test circuit to the scan chain, thereby enabling efficient signal routing without requiring complex direct connections between all test circuits and all scan chains.
3Measurement precision
If separate inspection is performed for each chip in a multi-chip package, then defect detection is thorough, but testing time and productivity are reduced
Solution Approach 1:
The patent enables continuous testing of multiple chips through the shared scan chain infrastructure. By allowing the first test circuit and second test circuit to operate sequentially or in coordination through the same scan chain, the system maintains continuous useful action for defect detection across multiple chips, thereby improving testing throughput without sacrificing detection accuracy.
Data Source
AI summary
An integrated circuit package for scan testing a semiconductor chip includes at least one first input pad configured to receive a first input signal, at least one chip connected to the first input pad, and at least one first output pad configured to receive a first output signal generated by the at least one chip, wherein each of the at least one chip includes at least one second input pad configured to receive a second input signal, a plurality of scan chains, a first test circuit and a second test circuit, which share the plurality of scan chains, and at least one second output pad configured to receive a second output signal from the first test circuit.