Shared Sense Amplifier DRAM Bank Layout for Smaller Die Area
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Solution Overview
Problem
Conventional DRAM devices have a large occupied area due to the presence of numerous sense amplifiers, which hinders the increase in the number of DRAM devices per wafer die and increases manufacturing costs.
Innovation Solution
The DRAM device architecture incorporates a bank group concept where memory banks are grouped, and sense amplifiers are connected to multiple bit line pairs via switch pairs, allowing them to operate on alternating bit line pairs during different row cycle time periods, reducing the number of required sense amplifiers and occupied area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional sense amplifier architecture is used, then memory operation reliability is ensured, but occupied area increases
Solution Approach 1:
Each sense amplifier is designed to handle multiple bit line pairs (BL0-BL3) through switch pairs, allowing a single sense amplifier to serve multiple memory banks. This multi-functionality reduces the total number of sense amplifiers needed while maintaining reliable memory operations across all banks.
Solution Approach 2:
The patent introduces dynamic switching mechanisms (switch pairs SW00-SW31) that dynamically connect sense amplifiers to different bit line pairs based on which memory bank is being accessed. This dynamic reconfiguration allows the same sense amplifier infrastructure to reliably serve multiple banks without interference, reducing overall area while maintaining operational reliability.
2Speed
If more sense amplifiers are used, then memory operation speed is improved, but occupied area increases
Solution Approach 1:
The dynamic switching architecture enables sense amplifiers to be rapidly reconfigured between different bit line pairs and memory banks. This dynamic capability allows the system to maintain high memory operation speeds by quickly switching between banks without requiring separate dedicated sense amplifiers for each bank, thus avoiding area expansion.
Solution Approach 2:
The patent implements periodic row cycle time periods (first row cycle, second row cycle) during which different sets of bit line pairs are actively connected to sense amplifiers. This periodic switching pattern ensures that memory operations proceed at high speed within each cycle while the same hardware infrastructure is reused across cycles, preventing area increase.
3Area of stationary object
If sense amplifiers are shared across multiple banks, then occupied area is reduced, but access time increases
Solution Approach 1:
The dynamic switch pairs enable rapid reconfiguration of the sense amplifier connectivity, allowing the system to quickly transition between accessing different memory banks. This dynamic switching occurs fast enough that the effective access time penalty is minimized, while still achieving significant area reduction through shared sense amplifier infrastructure.
Solution Approach 2:
The patent structures memory access in periodic row cycles where specific bit line pairs are activated in predetermined sequences. This periodic organization allows the system to efficiently manage shared sense amplifiers across multiple banks with predictable timing, preventing excessive access time delays while maintaining reduced area.
Data Source
AI summary
A dynamic random-access memory (DRAM) device includes a first physical memory area corresponding to a first memory mat, a second physical memory area corresponding to a second memory mat, bit line pairs, switch pairs and sense amplifiers. The first and second physical memory areas include memory cells of the first memory bank and memory cells of the second memory bank being arranged alternately. The sense amplifiers of the first memory bank are electrically connected to first-bank bit line pairs in the first and second physical memory areas during a first row cycle time period. The sense amplifiers are configured to perform a memory operation to the memory cells connected to the first-bank bit line pairs during the first row cycle time period.