Shared Sense Amplifier Write Driver Circuit Area Reduction
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Solution Overview
Problem
Conventional high-speed memory designs with separate sense amplifiers and write drivers are susceptible to leakage currents and occupy larger areas than desired.
Innovation Solution
A combined sense amplifier/write driver circuit is implemented, utilizing a set of four transistors and switches configured to operate in both read and write modes, sharing transistors to reduce area and prevent leakage currents by switching between modes based on control signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate large sense amplifiers and write drivers are used, then mismatch is reduced and write margins are improved, but area increases and leakage currents occur
Solution Approach 1:
The patent combines the sense amplifier and write driver into a single integrated circuit block that shares common transistors (specifically the first and second transistors connected to bit lines BL and BLB). This merging reduces the total area while maintaining the functional separation needed for both read and write operations, directly resolving the area penalty of using separate large circuits.
Solution Approach 2:
The shared transistors in the combined circuit serve dual purposes: they function as sense amplifier transistors during read operations and as write driver transistors during write operations. This multi-functionality allows the same hardware resources to be reused for both read and write functions, eliminating the need for separate dedicated circuits and reducing overall area.
2Reliability
If separate large sense amplifiers and write drivers are used, then mismatch is reduced and write margins are improved, but leakage currents increase
Solution Approach 1:
By merging the sense amplifier and write driver into a single circuit with shared transistors, the patent eliminates idle transistors that would otherwise generate leakage currents. The shared transistors are actively used in both read and write modes, preventing the leakage issues associated with separate circuits where transistors may remain in standby states.
Solution Approach 2:
The circuit design allows transistors to be dynamically switched between read and write functions, effectively recovering their utility rather than leaving them idle. The control logic ensures that transistors are actively utilized in their appropriate mode, preventing the leakage currents that would occur if separate circuits operated independently with unused components.
3Area of stationary object
If a combined sense amplifier/write driver is used, then area is reduced and leakage currents are eliminated, but circuit complexity increases
Solution Approach 1:
The combined circuit employs dynamic control signals (such as WR and WRB) that switch the operational mode of the shared transistors between read and write functions. This dynamic reconfiguration allows a single static circuit structure to perform multiple functions, reducing area while managing complexity through temporal separation of operations rather than spatial multiplication of components.
Data Source
AI summary
Systems and methods are provided for a sense amplifier/write driver circuit. A system includes a set of transistors responsive to a memory cell, the set of transistors configured to operate as a sense amplifier in a first mode and to operate as a write driver in a second mode. One or more switches are configured to switch the set of transistors from the first mode to the second mode based on a control signal. Particular transistors of the set of transistors are configured by the one or more switches to amplify and retain data at a pair of input/output nodes for a period of time in the first mode. The particular transistors are further configured by the one or more switches to drive data to the pair of input/output nodes in the second mode.