Shared Shift Register Unit for Opposite-Level Gate Driving
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Solution Overview
Problem
Existing display panels require a large number of clock signal lines due to the need for two groups of gate driving circuits to provide gate driving signals with opposite levels, increasing the frame width and complexity.
Innovation Solution
A shift register unit is introduced with a first and second shift register circuit that outputs shift signals with logically opposite active levels, sharing a signal terminal group to reduce the number of clock signal lines and simplify the gate driving circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two groups of gate driving circuits are used to provide gate driving signals with opposite levels, then the pixel driving circuits can operate correctly with LTPO technologies, but the number of clock signal lines increases and the frame width becomes larger
Solution Approach 1:
The patent combines two separate gate driving circuits into a single integrated gate driving circuit that uses one group of shift register circuits to generate both high-level and low-level gate driving signals. This merging reduces the number of clock signal lines and decreases the frame width while maintaining the ability to drive pixels with LTPO technologies.
Solution Approach 2:
The shift register circuit is designed to perform multiple functions: it generates both first gate driving signals with high-level active states and second gate driving signals with low-level active states. This multi-functional design eliminates the need for separate dedicated circuits for each signal type, reducing overall complexity and frame width.
2Reliability
If two groups of gate driving circuits are used to provide gate driving signals with opposite levels, then the pixel driving circuits can operate correctly with LTPO technologies, but the circuit complexity increases
Solution Approach 1:
The patent merges two separate gate driving circuits into one integrated circuit, reducing the total number of components and interconnections. This consolidation simplifies the overall circuit architecture while maintaining the functional capability to provide both high-level and low-level gate driving signals for LTPO pixel circuits.
Solution Approach 2:
The single gate driving circuit is designed with multi-functionality, using one group of shift register circuits to generate both types of gate driving signals. This universal design reduces circuit complexity by eliminating redundant components and simplifying the signal generation architecture.
3Reliability
If two groups of gate driving circuits are used to provide gate driving signals with opposite levels, then the pixel driving circuits can operate correctly with LTPO technologies, but the number of clock signal lines increases
Solution Approach 1:
The patent combines the clock signal line requirements of two separate gate driving circuits into a single shared set of clock signal lines. The integrated gate driving circuit uses one group of shift register circuits that can be driven by a common clock signal, thereby reducing the total number of clock signal lines needed while maintaining reliable operation of LTPO pixel circuits.
Solution Approach 2:
The shift register circuit is designed as a universal signal generator that produces both high-level and low-level gate driving signals using a single group of clock signal lines. This multi-functional capability reduces the quantity of clock signal lines required compared to having separate dedicated circuits for each signal type.
Data Source
AI summary
The present disclosure relates to a shift register unit, a gate driving circuit and a display panel. The shift register unit includes a first shift register circuit and a second shift register circuit. The first shift register circuit is coupled to a signal terminal group and a first output terminal, and is configured to output a first shift signal to the first output terminal in response to a signal of the signal terminal group. The second shift register circuit is coupled with the first shift register circuit, and the second shift register circuit is coupled to the signal terminal group and a second output terminal, and is configured to output a second shift signal to the second output terminal in response to the signal of the signal terminal group, An active level of the first shift signal and an active level of the second shift signal are logically opposite.