Shared Source Line MRAM Cell Layout for Density

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Solution Overview

Problem

Conventional magnetoresistive random access memory (MRAM) designs face challenges in reducing the area of individual MRAM cells due to the lack of direct and parallel overlap between source lines and bit lines, resulting in limited density improvements.

Innovation Solution

The proposed solution involves a magnetic memory device with a shared source line and a shared bit line configuration, where the source line extensions are coupled to the main source line and extend in a direction orthogonal to the bit line, allowing for a more compact cell design.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If conventional source line and bit line arrangement is used, then manufacturing is simpler, but cell area cannot be minimized

Engineering Contradiction:
ImproveMRAM cell areaVSAvoidlayout complexity
Core Design Contradiction:
Area of moving objectVSDevice complexity

Solution Approach 1:

The source line extension is configured to extend in a direction substantially orthogonal to the bit line direction, utilizing spatial arrangement in multiple dimensions to achieve overlap between source line and bit line. This orthogonal arrangement allows the source line extension to traverse under the bit line, minimizing cell area while maintaining manufacturability through standardized via and metal connections.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If source line and bit line are arranged parallel without overlap, then manufacturing is easier, but density cannot be improved

Engineering Contradiction:
Improvememory densityVSAvoidfabrication complexity
Core Design Contradiction:
Quantity of substanceVSEase of manufacture

Solution Approach 1:

The source line extension is positioned to extend under the bit line, creating a nested spatial relationship where one conductor traverses the space occupied by another. This nesting arrangement enables direct and parallel overlap between source line and bit line, increasing memory density while using standard via and metal fabrication processes to maintain ease of manufacture.

Inventive Principle:
Principle #7Nested doll (Nesting)

3Area of moving object

If shared source line configuration is used, then cell density increases, but pitch reduction is limited

Engineering Contradiction:
Improvecell pitchVSAvoidalignment precision
Core Design Contradiction:
Area of moving objectVSManufacturing precision

Solution Approach 1:

The source line extension acts as an intermediary structure that connects the main source line to the active area while extending under the bit line. This intermediary configuration enables pitch reduction by allowing the source line to be positioned closer to the landing pad, while the extended structure maintains proper electrical connections and alignment through its orthogonal arrangement.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enables a reduction in the pitch between the source line and the landing pad, as well as the bit line pitch, thereby enhancing the density of MRAM cells without increasing the complexity of the memory array layout.

Implementation Method 1

A magnetoresistive random access memory may be a semiconductor device where magnetic elements (MTJ elements) having MTJs utilizing a tunnel magneto resistance (TMR) effect are arranged in a matrix form as a memory cell

Methodology Applied
Scientific EffectTunnel magneto resistance (TMR) effect: Magnetoresistance

Data Source

PatentEP3890023B1Magnetic memory device having shared source line and bit line
Publication Date: 2025.04.16 UNITED MICROELECTRONICS CORP
  • EP3890023B1 patent drawingFigure 1
  • EP3890023B1 patent drawingFigure 2
  • EP3890023B1 patent drawingFigure 3

AI summary

A memory device includes a substrate; an active area extending along a first direction on the substrate; a gate line traversing the active area and extending along a second direction that is not parallel to the first direction; a source doped region in the active area and on a first side of the gate line; a main source line extending along the first direction; a source line extension coupled to the main source line and extending along the second direction; a drain doped region in the active area and on a second side of the gate line that is opposite to the first side; and a data storage element electrically coupled to the drain doped region. The main source line is electrically connected to the source doped region via the source line extension.