Shared-String Programming of Multiple Erase Blocks to Reduce Cell Disturb
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Solution Overview
Problem
Existing memory systems face challenges in efficiently programming multiple erase blocks coupled to a same string, leading to disturb-related issues such as increased bit error rates and data loss due to threshold voltage shifts in neighboring cells, especially during program and program verify operations.
Innovation Solution
The solution involves applying a seed voltage from both the source and drain sides of a string to program memory cells sequentially, using flexible adjustments in voltage levels and configurations to mitigate disturb, and implementing different page maps for erase blocks to avoid passing the seed voltage through already-programmed cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If seed voltage is applied from source side to program memory cells, then programming operation can be performed, but disturb is increased in neighboring cells due to electric field effects
Solution Approach 1:
The string of memory cells is divided into multiple segments (first string and second string) separated by a dummy word line. The first erase block is programmed in the first string while the second erase block is programmed in the second string. This segmentation isolates the programming operations, preventing the seed voltage from causing disturb in cells belonging to different erase blocks, thus resolving the contradiction between programming efficiency and neighboring cell disturbance.
Solution Approach 2:
A dummy word line is introduced as an intermediary element between the first and second erase blocks. This dummy word line acts as a barrier that separates the first string from the second string, preventing the seed voltage applied during programming of the first erase block from directly affecting the second erase block. The intermediary structure enables independent programming operations while minimizing harmful electric field effects across block boundaries.
2Productivity
If multiple erase blocks are programmed sequentially, then data can be written to all blocks, but bit error rates increase due to threshold voltage shifts
Solution Approach 1:
The memory structure is segmented into multiple independent strings separated by dummy word lines, allowing different erase blocks to be programmed simultaneously or independently. This segmentation prevents threshold voltage shifts in one block from propagating to other blocks, maintaining data integrity and reducing bit error rates while enabling comprehensive data writing to all blocks.
Solution Approach 2:
Different regions (first string and second string) are treated with different programming parameters and seed voltage applications tailored to their specific requirements. The local quality approach allows optimized programming for each erase block, preventing uniform disturb effects and maintaining higher reliability across all programmed data.
3Ease of operation
If seed voltage passes through already-programmed cells, then programming can continue, but threshold voltage shifts occur in neighboring cells
Solution Approach 1:
The string is segmented into multiple sections separated by dummy word lines, creating independent programming zones. The seed voltage is applied to program cells in one segment without needing to pass through already-programmed cells in other segments. This segmentation enables programming continuity across multiple erase blocks while maintaining precise threshold voltage control in each block by isolating the electric field effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces disturb effects, lowers bit error rates, and maintains data integrity by minimizing the electric field during programming and verify operations, allowing for efficient and reliable operation of multiple erase blocks within a memory system.
Implementation Method 1
The cells can include a storage node such as a floating gate or charge-trap layer which allows the cells to be programmed to store one or more bits by adjusting the charge on the storage node
Implementation Method 2
Generally, an erase operation (e.g., a 'block erase') is performed to erase all of the cells of a block together as a group
Implementation Method 3
Programming memory cells (e.g., of a block) of the 3D memory array involves imposing a seed voltage on (alternatively referred to as 'pre-charging') the strings and applying a programming voltage to a selected word line
Data Source
AI summary
A method can comprise applying, to program memory cells of a first erase block coupled to a first string of a memory array, a seed voltage through a sense line coupled to the first string. The method can further comprise applying, to program memory cells of the first erase block sequentially from a source side to a drain side, a respective programming voltage to access lines of the first erase block sequentially from a first access line of the first erase block to a second access line of the first erase block. The first access line can be located adjacent to one or more dummy access lines separating the first erase block from a second erase block coupled to the first string. The second access line can be located at the drain side of the first string.