Shared TAGE Tables for Instruction and Trace Caches
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Solution Overview
Problem
Trace caches in traditional processor designs face challenges due to high area and power consumption, and the cost associated with unexpected branch exits, which have impeded their practical implementation.
Innovation Solution
Implementing a trace cache that caches only traces with internal control transfer instructions that meet certain criteria, such as being 'stable' branches, and sharing branch predictor resources to improve performance and reduce complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a trace cache is implemented to improve instruction fetch bandwidth and reduce fetch power consumption, then processor performance is improved, but the area and power consumption of the trace cache and its control circuitry increase substantially
Solution Approach 1:
The trace cache is divided into multiple sets, with each set containing multiple ways. This segmentation allows the trace cache to be accessed in parallel through multiple ports, improving instruction fetch bandwidth without requiring a single large monolithic cache structure that would consume excessive area.
Solution Approach 2:
The branch predictor resources are shared between the trace cache and the instruction cache. The same branch predictor circuitry is used to predict branches for both trace cache hits and instruction cache misses, eliminating the need for separate branch predictor resources and reducing overall processor area.
2Productivity
If a trace cache is implemented to improve instruction fetch bandwidth, then processor performance is improved, but power consumption increases
Solution Approach 1:
The trace cache is segmented into multiple sets and ways that can be accessed in parallel. This allows the fetch operation to be distributed across multiple smaller cache units, reducing the power consumption of any single cache unit while maintaining high overall fetch bandwidth through concurrent access.
Solution Approach 2:
The branch predictor resources are shared between trace cache and instruction cache operations. By reusing the same branch predictor circuitry for both trace cache hits and instruction cache misses, the patent reduces redundant power consumption that would occur if separate branch predictor resources were allocated for each cache type.
3Productivity
If branch prediction resources are allocated for trace cache predictions, then trace cache performance is improved, but device complexity increases
Solution Approach 1:
The branch predictor resources are designed to serve dual purposes: predicting branches for trace cache hits and predicting branches for instruction cache misses. This multi-functional design improves trace cache performance with dedicated branch prediction support while avoiding the complexity increase that would result from implementing entirely separate branch prediction circuits.
Data Source
AI summary
Disclosed techniques relate to branch prediction and trace caching. A processor may include both an instruction cache and a trace cache configured to store instructions. A branch predictor may include one or more prediction tables (e.g., tagged geometric length (TAGE) tables) configured to predict directions of conditional control transfer instructions. Rather than including a separate branch predictor for branches in the trace cache, the processor may share the prediction table(s) for instruction cache and trace cache predictions. In particular, the processor may include an additional trace prediction lane configured to access the prediction table to predict a direction of a final control transfer instruction in a trace cached by the trace cache circuitry. This may advantageously provide accurate predictions with limited impacts to circuit area and power consumption, e.g., relative to a separate predictor for the trace cache.