Shared Test Interface for Multi-Core IC Pin Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Modern integrated circuits, particularly SoCs, face challenges with the JTAG test interface requiring multiple pins for each CPU core, leading to a high number of unnecessary pins and limitations in signal propagation delay due to the JTAG standard's finite state machine definition and signal edge requirements.
Innovation Solution
An integrated circuit with a test interface that uses an interface module with a serial interface to transmit data via one signal line per content category, reducing the number of pins required and allowing data to be transmitted outside the chip more quickly than the JTAG standard, while maintaining compatibility with existing applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a JTAG test interface with multiple pins is used for each CPU core, then testing capability is improved, but the number of pins required increases
Solution Approach 1:
The patent combines multiple JTAG test interfaces for different CPU cores into a single shared test interface. The interface module can be connected to multiple TAP controllers, allowing one physical interface to serve multiple testing purposes, thereby reducing the total number of pins required while maintaining full testing capability for all CPU cores.
Solution Approach 2:
The test interface is designed with multi-functionality to handle testing for multiple CPU cores and different test scenarios through a single interface. The interface module can dynamically switch between different TAP controllers and test modes, making one interface serve universal testing needs that previously required multiple dedicated interfaces.
2Adaptability or versatility
If the JTAG standard's finite state machine definition is used, then compatibility with existing software is improved, but signal propagation delay increases
Solution Approach 1:
The interface module acts as an intermediary between the external test equipment and the TAP controllers. It translates and mediates the communication, allowing faster signal transmission while maintaining compatibility with the JTAG finite state machine protocol. The intermediary handles the protocol conversion and timing adjustments, enabling both speed improvement and software compatibility.
3Reliability
If multiple pins are used for test interface, then testing of multiple CPU cores is improved, but chip package space increases
Solution Approach 1:
The patent merges multiple dedicated test interfaces into a single shared interface module that can service multiple CPU cores. This consolidation reduces the number of pins required from four pins per CPU core to a single shared interface, significantly reducing the chip package area occupied by test interface connections while maintaining the ability to test all CPU cores.
Data Source
AI summary
An integrated circuit having a subordinate test interface and method for transmitting digital data is disclosed. The integrated circuit includes at least one test interface that is adapted to write and read data in and from a data memory, the at least one test interface includes, for transmitting and receiving data of different content categories, one signal line each for every content category. The integrated circuit further includes an interface module for receiving and transmitting data, and that the interface module is, via the signal lines, connected with the test interface for transmitting the data of the different content categories.