Shared Deep Trench Isolation Layout for Compact BCD Isolation
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Solution Overview
Problem
The integration of bipolar, CMOS, and DMOS devices on a single chip for BCD technology faces challenges in electrical isolation due to the need for significant layout area for deep trench isolation structures, which increases the chip design footprint and can lead to damage from high voltage devices to low voltage devices.
Innovation Solution
A single, continuous deep trench isolation structure with rounded portions and specific intersections is used to reduce the isolation structure size while maintaining sufficient electrical isolation, sharing the isolation structure among BCD layout areas and reducing sidewall oxide thickness asymmetry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a deep trench isolation structure is used to provide electrical isolation between BCD layout areas, then electrical isolation between high and low voltage devices is improved, but the layout area and chip design footprint increase
Solution Approach 1:
The patent merges multiple isolation functions into a single continuous deep trench isolation structure that serves multiple BCD layout areas simultaneously. This shared isolation structure reduces the total layout area compared to providing separate isolation structures for each layout area, while maintaining sufficient electrical isolation between high and low voltage devices.
Solution Approach 2:
The patent introduces rounded portions at intersections of the deep trench isolation structure with BCD layout areas. This curvature reduces the overall footprint of the isolation structure by eliminating sharp corners that would require additional layout space, while the rounded geometry maintains effective electrical isolation by ensuring continuous coverage at critical transition points.
2Reliability
If a large deep trench isolation structure is used to ensure sufficient electrical isolation, then breakdown voltage protection is improved, but the chip real estate is unnecessarily consumed
Solution Approach 1:
The patent applies isolation structures selectively at specific locations where electrical isolation is most critical, rather than uniformly across the entire chip. The deep trench isolation structure is positioned to provide local quality enhancement at interfaces between BCD layout areas, ensuring breakdown voltage protection where needed while minimizing consumption of chip real estate in non-critical regions.
Data Source
AI summary
Devices and methods of manufacture for a deep trench layout area-saving semiconductor structure for use with bipolar-CMOS-DMOS (BCD) devices. A semiconductor device may comprise a first BCD device formed within a first perimeter of a first BCD layout area, and a deep trench isolation structure defining the first perimeter of the first BCD layout area, in which the deep trench isolation structure may comprise a first rounded corner that may define a first corner of the first BCD layout area. A semiconductor device may comprise, a substrate, BCD device formed on the substrate, and a deep trench isolation structure laterally surrounding the BCD device. The deep trench isolation structure, with respect to a top-down view, may comprise vertical portions, horizontal portions, a âTâ-shaped intersection connecting at least one vertical portion and at least one horizontal portion, and a cross-shaped intersection connecting two vertical portions and two horizontal portions.