Shared Vector Operator Architecture for Multi-Core Scalar Processing
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Solution Overview
Problem
Current processors that implement vector operations suffer from idle states and occupy large semiconductor chip surface area due to the need for extensive circuits, leading to inefficiencies and increased space requirements.
Innovation Solution
A processor architecture where a shared vector operator processes vector operations across multiple cores, with each core also having a scalar operator for scalar operations, and a scheduler to manage instruction delivery and prioritize processing, along with a register merger to enhance vector register efficiency by merging and resizing registers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a processor provides vector processing capability, then processing speed for vector operations is improved, but the processor occupies a large space on semiconductor chip surface
Solution Approach 1:
The patent merges vector processing capability into a shared resource that can be accessed by multiple scalar processing cores. Instead of each core having its own vector processor, the vector operator is consolidated and shared across multiple cores, reducing the total circuit area while maintaining vector processing speed when needed.
Solution Approach 2:
The shared vector operator is designed to serve multiple scalar cores, making it a universal resource that can handle vector operations for any of the cores. This multi-functional design allows one vector processor to replace what would otherwise require multiple separate vector processors, reducing chip area while preserving processing capability.
2Adaptability or versatility
If a processor provides vector processing capability, then vector operations can be performed, but the processor experiences idle states and reduced efficiency
Solution Approach 1:
The system dynamically allocates the shared vector operator to different scalar cores based on the current execution needs. The vector processor transitions between serving different cores or remaining idle only when no vector operations are pending, optimizing resource utilization and reducing idle states through dynamic task assignment.
Solution Approach 2:
The shared vector operator is designed to maintain continuous useful action by quickly transitioning between serving different scalar cores. When one core finishes its vector operations, the vector processor immediately becomes available for the next core that needs vector processing, minimizing idle time and maintaining continuous productive operation.
3Productivity
If vector processing is implemented, then multiple data can be operated on by single instruction, but scalar operations are delayed until vector operations complete
Solution Approach 1:
The processing architecture is segmented into independent scalar processing cores and a separate shared vector operator. This segmentation allows scalar and vector operations to proceed independently without blocking each other, as each scalar core can execute scalar instructions while the vector operator handles vector instructions separately, eliminating the delay where scalar operations must wait for vector operations to complete.
Data Source
AI summary
An operation processing apparatus is provided. The operation processing apparatus includes a vector operator and cores. The vector operator processes a vector operation with respect to an instruction that uses the vector operation, and each core includes a scalar operator that processes a scalar operation with respect to an instruction that does not use the vector operation. The vector operator is shared by the cores.