Shared XOR-XNOR Comparison Circuit for Faster DRAM ECC
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Solution Overview
Problem
As semiconductor memory technologies advance and memory density increases, errors in Dynamic Random Access Memory (DRAM) storage become more prevalent, necessitating effective error detection and correction techniques, but existing solutions are inefficient in terms of circuit area and operation speed.
Innovation Solution
A comparison system is developed that incorporates a common module for both XOR and XNOR logical operations, reducing circuit area while allowing for larger areas for individual logical units, thereby enhancing driving capability and operation speed for error detection and correction in DRAM systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate circuits are used for XOR and XNOR operations, then operational reliability is improved, but circuit area and device complexity increase
Solution Approach 1:
The patent combines XOR and XNOR circuits into a single integrated structure where the second logical unit shares the common module with the first logical unit. This merging reduces overall circuit area while maintaining the functional integrity and reliability of both operations through shared infrastructure.
Solution Approach 2:
The common module is designed to serve dual purposes: it supports both the first logical unit for XOR operations and the second logical unit for XNOR operations. This multi-functionality allows a single circuit component to perform multiple logical operations, reducing the total number of components needed while preserving operational reliability.
2Speed
If larger area is allocated to logical units, then driving capability and operation speed improve, but total circuit area increases
Solution Approach 1:
By merging the XOR and XNOR circuits into a single structure with a shared common module, the patent creates space efficiency that allows larger area allocation to the logical units themselves. This enables enhanced driving capability and faster operation speeds without proportionally increasing the total circuit footprint.
Solution Approach 2:
The universal common module serves both logical units, reducing redundant infrastructure and freeing up area that can be allocated to the computational logic itself. This multi-functional design optimizes the ratio of computational area to support area, improving operation speed within constrained total area.
Data Source
AI summary
Embodiments of the disclosure provide a comparison system including at least one comparison circuit, the comparison circuit including: a common circuit, connected to a power supply signal and a ground signal, and configured to control output of the power supply signal or the ground signal based on a first signal and a second signal which are inverted; a first logical circuit, connected to the common circuit, and configured to receive a third signal and a fourth signal which are inverted, and output a first operation signal which is an exclusive OR (XOR) of the first signal and the third signal; and a second logical circuit, connected to the common circuit, and configured to receive the third signal and the fourth signal, and output a second operation signal which is a not exclusive OR (XNOR) of the first signal and the third signal.