Sharp-Corner Interconnect Features for Lower Contact Resistance

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Solution Overview

Problem

As MOS devices downscale, the optical proximity effect leads to rounded line ends of interconnect features, reducing effective contact areas and increasing contact resistance due to smaller line-widths and spacing between interconnect features.

Innovation Solution

The process involves forming FinFETs and interconnect features with sharper corners by cutting metal gates and source/drain contact plugs, using techniques like lithography and etching to create openings that extend beyond the edges of gate stacks and contact plugs, and filling these with dielectric materials to reduce line-end rounding and enhance contact areas.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If optical proximity effect is considered in conventional interconnect formation, then line-widths and spacing can be controlled, but line ends become rounded and effective contact area is reduced

Engineering Contradiction:
Improveline-end sharpnessVSAvoideffective contact area
Core Design Contradiction:
Manufacturing precisionVSArea of stationary object

Solution Approach 1:

The patent applies preliminary action by forming a mandrel structure with extended ends before the main interconnect formation process. The mandrel extends beyond the gate stack edges, and spacers are formed on the mandrel sidewalls. This preliminary structure ensures that subsequent etching and filling processes create sharp-cornered interconnect features with adequate contact area, preventing the rounding issue that would otherwise occur during normal fabrication.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If downscaling of MOS devices is pursued, then device density increases, but optical proximity effect worsens and contact resistance increases

Engineering Contradiction:
Improvedevice densityVSAvoidcontact resistance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent segments the interconnect formation process into distinct stages: mandrel formation, spacer deposition, and selective etching. This segmentation allows independent optimization of each step. The mandrel is formed first, then spacers are added, and finally the structure is etched to create the final interconnect pattern. This segmented approach enables sharp corners and adequate contact area even at scaled dimensions, maintaining reliability while achieving high device density.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a mandrel structure as an intermediary element that facilitates the formation of sharp-cornered interconnect features. The mandrel serves as a temporary structure that defines the geometry, and spacers formed on its sidewalls further refine the shape. This intermediary mandrel-spacer system enables precise control over line-end geometry, ensuring sharp corners and adequate contact area during downscaling.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of manufacture

If conventional interconnect features are formed, then fabrication process is simple, but contact area loss and Joule heating increase

Engineering Contradiction:
Improvefabrication complexityVSAvoidJoule heating
Core Design Contradiction:
Ease of manufactureVSLoss of energy

Solution Approach 1:

The patent changes the geometric parameters of the interconnect features by using a mandrel structure with extended ends and forming spacers on its sidewalls. This parameter change results in sharp corners and increased effective contact area compared to conventional rounded features. The additional fabrication steps (mandrel formation and spacer deposition) are offset by the elimination of contact resistance issues and reduced Joule heating, making the overall process advantageous despite slightly increased complexity.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12002865B2Interconnect features with sharp corners and method forming same
Publication Date: 2024.06.04 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12002865B2 patent drawing
  • US12002865B2 patent drawing
  • US12002865B2 patent drawing

AI summary

A method includes depositing a dielectric layer, depositing a plurality of mandrel strips over the dielectric layer, and forming a plurality of spacers on sidewalls of the plurality of mandrel strips to form a plurality of mask groups. Each of the plurality of mandrel strips and two of the plurality of spacers form a mask group in the plurality of mask groups. The method further includes forming a mask strip connecting two neighboring mask groups in the plurality of mask groups, using the plurality of mask groups and the mask strip collectively as an etching mask to etch the dielectric layer and to form trenches in the dielectric layer, and filling a conductive material into the trenches to form a plurality of conductive features.