Shielded Conductive Pillar Assembly for High-Density Die Interconnects
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Solution Overview
Problem
Conventional microelectronic assemblies face challenges in efficiently communicating large numbers of signals between IC dies due to small die sizes, thermal constraints, and power delivery limitations, leading to reduced bandwidth, increased latency, and larger package sizes.
Innovation Solution
The proposed microelectronic assembly incorporates a package substrate with multi-layer die subassemblies and shield structures, featuring conductive pillars and interconnects with optimized pitch and shielding to enhance signal speed and power delivery while reducing package size, utilizing advanced lithography and manufacturing processes to achieve higher density interconnects and improved design flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional substrates are used for IC die coupling, then manufacturing and material constraints are satisfied, but interconnect pitch is constrained leading to reduced bandwidth
Solution Approach 1:
The patent transitions from planar interconnect routing to three-dimensional vertical stacking with through-silicon vias (TSVs), enabling signals to traverse multiple layers and significantly increasing bandwidth without increasing lateral pitch constraints
Solution Approach 2:
The substrate is divided into multiple layers with independent interconnect routes, allowing parallel signal paths and increasing effective bandwidth while maintaining manufacturable pitch dimensions in each layer
2Speed
If thermal constraints are reduced to increase signal speed, then bandwidth improves, but power delivery limitations and signal integrity deteriorate
Solution Approach 1:
Ground shield structures are introduced as intermediary elements between signal traces to provide electromagnetic shielding and reduce crosstalk, enabling higher signal speeds without compromising power integrity or signal quality
Solution Approach 2:
Different regions of the substrate are assigned different functional qualities - signal regions optimized for high-speed transmission and ground regions optimized for power delivery and shielding, allowing simultaneous optimization of speed and power characteristics
3Volume of moving object
If package size is reduced for compact applications, then device footprint decreases, but interconnect density and signal routing capabilities are constrained
Solution Approach 1:
The patent utilizes vertical stacking with multiple substrate layers and TSVs to achieve high interconnect density in the vertical dimension, allowing compact lateral package footprint while maintaining high routing capacity
Solution Approach 2:
Multiple interconnect layers and functional blocks are nested vertically within the package structure, with each layer containing complete interconnect systems, enabling high density integration in a compact volume
4Reliability
If shield structures are added to reduce signal crosstalk, then signal integrity improves, but device complexity and manufacturing difficulty increase
Solution Approach 1:
Ground shield structures are merged with existing substrate layers and interconnect routing, integrating shielding functionality into the standard multi-layer substrate architecture rather than adding separate shielding components
Solution Approach 2:
The ground layers serve multiple functions simultaneously - providing electromagnetic shielding for signal integrity, establishing reference potentials, and enabling power delivery, thereby reducing the need for dedicated shielding structures
Data Source
AI summary
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a first die having a first surface and an opposing second surface, wherein the first die is embedded in a first dielectric layer, wherein the first surface of the first die is coupled to the second surface of the package substrate, and wherein the first dielectric layer is between a second dielectric layer and the second surface of the package substrate; a second die having a first surface and an opposing second surface, wherein the second die is embedded in the second dielectric layer, and wherein the first surface of the second die is coupled to the second surface of the package substrate by a conductive pillar; and a shield structure that at least partially surrounds the conductive pillar.