Shielded Semiconductor Package for 2.5D Stacked Integration
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Solution Overview
Problem
In 2.5 D/3D stacked die packaging systems, power supply noise jitter and electromagnetic interference (EMI) are significant issues due to the placement of power delivery decoupling capacitors and communication devices, which hinder device miniaturization and performance.
Innovation Solution
A shielded semiconductor package design featuring a substrate, interposer, shield frame with conductive layers, and embedded components, which reduces power inductance loop and EMI by positioning decoupling capacitors closer to the devices and using a conductive shield to isolate components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If decoupling capacitors are placed far from stacked IC devices on package substrate, then package area is reduced, but power supply noise jitter increases
Solution Approach 1:
The patent transitions from planar placement on package substrate to three-dimensional placement on the interposer surface, allowing capacitors to be positioned in close proximity to stacked IC devices vertically rather than horizontally, thus reducing power loop inductance while maintaining compact package footprint
Solution Approach 2:
The interposer serves as an intermediary platform between the package substrate and stacked IC devices, providing a dedicated surface for capacitor placement that optimizes power delivery paths without compromising package area or signal integrity
2Object-affected harmful factors
If device-to-device spacing is increased to mitigate EMI, then EMI shielding is improved, but interconnect length increases causing lossy transmission
Solution Approach 1:
The patent extracts the EMI shielding function from the interconnect structure itself and implements it through dedicated shield frames and conductive shielding layers positioned between communication devices, allowing devices to be placed in close proximity without compromising EMI performance
Solution Approach 2:
Shield frames and conductive shielding layers act as intermediary structures between communication devices, providing EMI protection while maintaining short interconnect lengths and preserving signal transmission quality
3Reliability
If more decoupling capacitors are added to suppress power supply noise, then power noise is reduced, but package real estate is consumed
Solution Approach 1:
The patent utilizes the vertical dimension on the interposer surface to place multiple decoupling capacitors in close proximity to stacked IC devices, achieving superior power noise suppression without consuming additional horizontal package real estate
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves platform miniaturization, improved signal integrity, reduced power supply noise jitter, and enhanced EMI shielding, allowing for increased device integration and higher package ball grid array input/output density.
Implementation Method 1
a conductive shield layer on the shield frame... reduced power inductance loop and EMI by positioning decoupling capacitors closer to the devices and using a conductive shield to isolate components
Implementation Method 2
power delivery decoupling capacitors are disposed far apart from stacked integrated circuit devices... escalated power supply noise jitter... reduced power supply noise jitter
Data Source
AI summary
The present disclosure relates to a semiconductor package that may include a substrate, an interposer coupled to the substrate, a shield frame including at least one frame recess and at least one opening positioned over the interposer, a conductive shield layer on the shield frame, and a plurality of components coupled to the interposer.