Shift Register Layout for Opposite-Potential Gate Drive Signals
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing gate drive circuits struggle to simultaneously provide positive-phase and negative-phase gate driving signals with opposite potentials, which is necessary for low temperature polycrystalline oxide (LTPO) processes to reduce pixel circuit leakage and flicker, while occupying excessive layout space and being susceptible to clock signal delays.
Innovation Solution
A shift register design with an input circuit, intermediate circuit, and output circuit, utilizing NAND gates, inverters, and control transistors to generate and stabilize opposite potential output signals without excessive layout, using P-type and N-type transistors to ensure stable and simultaneous output of opposite potential signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing gate drive circuits are used to simultaneously provide positive-phase and negative-phase gate driving signals, then the display performance can be improved by reducing pixel circuit leakage and flicker, but the layout space occupied is excessive and the circuit is susceptible to clock signal delays
Solution Approach 1:
The gate drive circuit is segmented into three functional modules: input circuit, intermediate circuit, and output circuit. Each module has a specific function - the input circuit receives clock signals and generates intermediate signals, the intermediate circuit processes these signals with controlled delays, and the output circuit generates the final opposite-phase output signals. This segmentation allows for compact layout while maintaining the required functionality for reducing pixel circuit leakage and flicker.
Solution Approach 2:
The intermediate circuit acts as an intermediary between the input circuit and output circuit. It includes intermediate nodes and delay elements that mediate the signal transmission, allowing precise control over signal timing and phase relationships. This intermediary structure enables the generation of opposite-phase signals with minimized layout space and reduced susceptibility to clock signal delays.
2Reliability
If existing gate drive circuits are used to simultaneously provide positive-phase and negative-phase gate driving signals, then the display performance can be improved by reducing pixel circuit leakage and flicker, but the circuit is susceptible to clock signal delays
Solution Approach 1:
The input circuit performs preliminary processing of clock signals before they reach the output circuit. By pre-generating intermediate signals with controlled phases and amplitudes, the system compensates for potential delays in the output stage. This preliminary action ensures that the final opposite-phase signals are generated with minimal overall delay and reduced susceptibility to clock signal variations.
Solution Approach 2:
The intermediate circuit includes feedback paths that monitor signal phases and adjust timing accordingly. This feedback mechanism compensates for clock signal delays by dynamically adjusting the phase relationships between intermediate nodes, ensuring stable and synchronized opposite-phase output signals that are less susceptible to clock signal delay variations.
3Area of stationary object
If a compact shift register design is used to reduce layout space, then the layout space requirements are reduced, but the circuit may become more susceptible to clock signal delays and signal instability
Solution Approach 1:
Different regions of the compact shift register are designed with locally optimized characteristics. The input circuit region focuses on signal conditioning, the intermediate circuit region emphasizes precise delay control with buffered signal paths, and the output circuit region prioritizes signal driving capability. This local quality optimization maintains signal stability throughout the compact structure by tailoring each region's design to its specific functional requirements.
Solution Approach 2:
The compact shift register incorporates dynamic signal buffering and phase adjustment mechanisms in the intermediate circuit. These dynamic elements actively maintain signal integrity despite the reduced layout space, adjusting signal levels and phases in real-time to compensate for the compact design's potential vulnerabilities to clock signal delays and instability.
Data Source
AI summary
Provided is a shift register. The shift register comprising: an input circuit, an intermediate circuit and an output circuit; the input circuit is connected to a first power supply terminal, a second power supply terminal, an input voltage terminal and a first clock signal terminal, and the input circuit is configured to output an intermediate input signal to the intermediate circuit; the intermediate circuit is connected to the first power supply terminal, the second power supply terminal and a second clock signal terminal, and the intermediate circuit is configured to output a first node signal to the output circuit; and the output circuit is connected to the first power supply terminal, the second power supply terminal, a first output terminal and a second output terminal, and the output circuit is configured to output a first output signal and a second output signal.