Shift Register Output Circuit Alternating Clock Phases
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Solution Overview
Problem
The stability and service lifetime of shift registers in gate driver circuits are compromised due to continuous high-level signal flow through output transistors, leading to transistor characteristic drift and reduced display panel longevity.
Innovation Solution
A shift register design incorporating multiple switch transistors and capacitors, with alternating control circuits and output channels, uses signals with the same cycle and opposite phases to manage the drive signal output, preventing prolonged operation of individual transistors and enhancing stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single output transistor continuously provides high-level signals to the drive signal output terminal, then the shift register can maintain continuous operation, but the transistor characteristic drifts and service lifetime is shortened
Solution Approach 1:
The patent divides the output stage into multiple transistors (first output transistor and second output transistor) that operate alternately. The first output transistor outputs high-level signals during the first clock phase while the second output transistor outputs high-level signals during the second clock phase. This segmentation allows continuous operation while each transistor rests during the other's active period, preventing characteristic drift and extending service lifetime.
2Stability of the object's composition
If the gate of the output transistor remains at the same bias for a long period of time, then the high-level signal can be maintained, but the transistor characteristic drifts and service lifetime is reduced
Solution Approach 1:
The patent implements periodic action by alternating the operation between the first output transistor and the second output transistor based on clock signals with opposite phases. During the first clock phase, the first output transistor is activated while the second is deactivated. During the second clock phase, the roles are reversed. This periodic switching ensures that no single transistor remains in the same bias state for extended periods, preventing characteristic drift while maintaining continuous high-level signal output.
Data Source
AI summary
A shift register, a method for driving the same, a gate driver circuit, and a display device are provided. The shift register includes an input circuit, a reset circuit, a first control circuit, a first output circuit, and a second output circuit, where the first output circuit includes two output channels, where one channel is that under the joint control of signals of a first clock signal terminal and a first node, a signal of a first clock signal terminal is provided to a drive signal output terminal of the shift register, and the other channel is that under the joint control of signals of the second clock signal terminal and the first node, a signal of a second clock signal terminal is provided to the drive signal output terminal.