Shift Register Timing for Flexible Display Scan Output
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The scan signals output by existing scanning circuits in display panels have low flexibility, leading to increased border area and signal delay, making it difficult to meet the application requirements of display panels where odd- and even-numbered row pixel circuits are connected to different data lines.
Innovation Solution
A shift register design incorporating multiple clock signals with controlled delays and overlapping pulses, allowing for flexible control of scan signal output by introducing additional clock signals and modules to manage signal timing and overlap, thereby enhancing the flexibility of the gate drive circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional single-clock shift register design is used, then device complexity is reduced, but scan signal flexibility is insufficient
Solution Approach 1:
The shift register is divided into multiple control modules (first control module, second control module, third control module) that independently process different clock signals. Each module can be configured with different clock signal connections, allowing flexible scan signal output patterns without requiring complete redesign of the entire shift register structure.
Solution Approach 2:
The shift register circuit is designed to support multiple operating modes by connecting different clock signal terminals to different functional modules. The same physical circuit can output non-overlapping scan signals, overlapping scan signals, or other timing patterns by reconfiguring clock signal connections, making it universally applicable to various display panel configurations.
2Loss of time
If border area is increased to accommodate scanning circuits, then signal delay is reduced, but display panel area efficiency decreases
Solution Approach 1:
The scanning circuit uses dynamic clock signal timing control where the effective level pulses of different clock signals are deliberately delayed relative to each other. This dynamic timing adjustment allows the circuit to maintain proper signal propagation without requiring additional physical space, reducing border area while controlling signal delay through temporal rather than spatial means.
3Adaptability or versatility
If clock signals are delayed to achieve non-overlapping output, then scan signal flexibility is improved, but timing control complexity increases
Solution Approach 1:
Delay circuits are introduced as intermediary components between the clock signal terminals and the control modules. These delay circuits automatically adjust the timing of clock signals, creating the required non-overlapping or overlapping output patterns without requiring complex control logic. The delay circuits act as mediators that simplify the overall timing control by handling the complexity of pulse synchronization internally.
Data Source
AI summary
Embodiments of the present application disclose a shift register, and a gate drive circuit and a driving method therefor. A first control module is configured to control, based on a signal of a first clock signal terminal, a signal of a second clock signal terminal, and a level of a second node, an initial signal and a first level signal to be transmitted to a first node. A second control module controls, based on the initial signal and a signal of a third clock signal terminal, a second level signal and the signal of the third clock signal terminal to be transmitted to the second node. An output module controls, based on a level of the first node, the signal of the second clock signal terminal to be transmitted to an output terminal of the shift register.