Shift Register Star Controller for SoC Core Testing
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Solution Overview
Problem
Existing semiconductor test systems face challenges in efficiently testing and debugging multiple cores within a System on Chip (SoC) after they are installed, as methods like BIST and TDC require significant design overhead and multi-site testing is costly, with current methods being limited in scope and efficiency.
Innovation Solution
A semiconductor test system and method utilizing shift registers, multiplexers, and controllers to selectively test and debug cores within a DUT, employing IEEE 1149.1 and IEEE 1500 standards, with a star controller performing linear feedback shift operations to manage test signals and select cores for testing, reducing the need for extensive I/O pins and overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If BIST and TDC methods are used to test DUTs, then testing capability is provided, but design overhead and ATE requirements become relatively large
Solution Approach 1:
The shift register is designed to perform multiple functions: it can operate in normal mode for data storage/transfer and in test mode for BIST operations. The same hardware structure serves both operational and testing purposes, eliminating the need for separate dedicated test structures and reducing design overhead while maintaining full testing capability
Solution Approach 2:
The system implements built-in self-test capability where the shift register contains an internal feedback mechanism that automatically generates test patterns and evaluates core functionality without requiring external ATE intervention. The register uses its own structure to generate and analyze test sequences, reducing external testing requirements
2Productivity
If multi-site test is used to test N SoCs simultaneously, then testing efficiency is improved, but testing costs become relatively large
Solution Approach 1:
Multiple DUTs share a common output path through the star controller and single TDO pin. The system combines multiple test outputs into a single communication channel using time-division or selective activation methods, allowing N devices to be tested through one output interface, thereby reducing the number of required ATE channels and associated costs while maintaining simultaneous testing capability
3Reliability
If individual cores are tested separately, then core functionality is verified, but SoC integration issues cannot be detected
Solution Approach 1:
The shift register and star controller provide a universal testing interface that works for individual core testing and integrated SoC testing. The same BIST infrastructure can selectively test single cores in isolation or multiple cores in their integrated configuration, allowing verification of both individual functionality and system-level integration issues without requiring separate test setups
Data Source
AI summary
A method of testing a plurality of DUTs includes providing a plurality of shift registers to test a plurality of cores in each DUT, supplying test input data, a test mode input signal, a test clock signal, and a test reset signal to the shift registers and cores, receiving a master bit, a first control value, and a second control value, based on the test input data and the test mode input signal, according to the test clock signal and the test reset signal, selecting at least one core and a test method, according to the first control value, selecting a target DUT according to the master bit or the second control value, simultaneously testing and debugging the selected core according to the test method, and outputting the test data output of the target DUT to check a result of the testing when an output enable signal is received.