Shock Recovery Circuit for PLL Clock Continuity Under Mechanical Shock

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Solution Overview

Problem

Mechanical shock events can disturb mechanical oscillating sensors used in clock generation systems, leading to system clock failures and data discontinuities.

Innovation Solution

A shock recovery circuit that includes a PLL monitor, acceleration monitor, and controller to detect impending shock events by monitoring PLL and acceleration signals, switching the system clock source from a mechanical oscillating sensor to an internal oscillator during disturbances, and ensuring continuous operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a mechanical oscillating sensor is used to generate the system clock, then the system can achieve precise timing and frequency control, but the system becomes susceptible to clock failure during mechanical shock events

Engineering Contradiction:
Improveclock precisionVSAvoidclock reliability
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The shock recovery circuit proactively monitors acceleration data and PLL status signals to detect impending or ongoing shock events before they cause complete clock failure. By switching to the oscillator clock source in advance or during the shock event, the system prevents data discontinuities and maintains continuous operation

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The shock recovery circuit acts as an intermediary between the mechanical oscillating sensor and the system, monitoring both acceleration data and PLL status. It selectively switches between the PLL clock source and oscillator clock source based on shock detection, protecting the system from mechanical shock effects while maintaining clock precision during normal operation

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the system switches to an oscillator clock during shock events, then system continuity is maintained, but additional circuit complexity is introduced

Engineering Contradiction:
Improvesystem continuityVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The shock recovery circuit performs multiple functions: it monitors acceleration data, analyzes PLL status signals, detects shock events, and controls the clock source switching. This multi-functional approach consolidates what could be separate circuits into a single integrated unit, reducing overall system complexity while maintaining reliability

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The clock generation system is self-monitoring and self-correcting. The shock recovery circuit automatically detects shock events through acceleration and PLL status monitoring, and autonomously switches between clock sources without external intervention. The system serves itself by detecting and recovering from its own vulnerabilities

Inventive Principle:
Principle #25Self-service

Data Source

PatentEP4641929A1Shock recovery
Publication Date: 2025.10.29 STMICROELECTRONICS INT NV
  • EP4641929A1 patent drawingFigure 1
  • EP4641929A1 patent drawingFigure 2~3
  • EP4641929A1 patent drawingFigure 4~5

AI summary

A shock recovery circuit (170, 300) is disclosed. The circuit includes a phase locked loop, PLL, monitor circuit (310, 410) configured to receive at least one of a PLL input clock (CKPLLIN, PLL_IN) and a PLL feedback clock (CKPLLFB, PLL_FB), and to generate a PLL status signal (PLLSTAT) based on at least one of the PLL input clock and the PLL feedback clock, the PLL status signal indicating whether a shock event has occurred; an acceleration monitor circuit (320, 500) configured to receive acceleration data (DATA), and to generate an acceleration status signal (ACCSTAT) based on the acceleration data, the acceleration status signal indicating whether the shock event has occurred; and a controller (330), configured to receive the PLL status signal and the acceleration status signal, generate an enable signal (EN) indicating whether a mechanical oscillating sensor (140) generating the PLL input clock is to operate, and generate a multiplexer signal (CTRL, CKMUX) indicating whether a system clock (CKSYS) is to be generated based on the PLL feedback clock.