SiC Power Semiconductor Cell Layout for Deep Ion Implantation
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Solution Overview
Problem
The deep ion implantation required in SiC power devices leads to a tilted resist pattern, causing a collapsed impurity region profile and decreased chip performance due to the thick resist mask needed.
Innovation Solution
A power semiconductor device with first and second unit cells cyclically arranged in a matrix pattern, along with a plurality of end cells, where the number of arrangement cycles changes depending on repetition coordinates, and each unit cell is adjacent to end cells, differing in electric properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If a thick resist mask is used for deep ion implantation, then the ion implantation depth is sufficient, but the side surface of the resist pattern tilts causing impurity region profile collapse
Solution Approach 1:
The patent divides the resist mask into multiple thin layers (first resist layer and second resist layer) instead of using a single thick resist mask. This segmentation allows each layer to maintain structural integrity while achieving the required total thickness for deep ion implantation, preventing the side surface tilting and profile collapse that occurs with a single thick resist layer.
Solution Approach 2:
The patent employs a nested structure where the first resist layer and second resist layer are stacked one on top of the other. The ion implantation process penetrates through both layers, with the nested arrangement providing structural support that prevents tilting while enabling deep implantation, effectively combining the benefits of multiple thin layers with the required implantation depth.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the performance of the power semiconductor device by preventing the collapse of the impurity region profile and maintaining chip performance.
Implementation Method 1
In the SiC power device, ions tend to be deeply implanted in order to moderate an insulator electric field
Data Source
AI summary
A performance of a power semiconductor device is improved. A power semiconductor device including unit cells UR and UL cyclically arranged in an X direction and a Y direction perpendicular to each other and a plurality of end cells is used. The unit cells UR and UL are alternately arranged in the X direction, the plurality of end cells include an X-end cell XL, Y-end cells YR and YL, an XY-end cell XY1L, and an XY-end cell XY2L for an optional region, each number of arrangement cycles of the unit cells UR and UL in the Y direction changes depending on repetition cycle coordinates in the X direction, each of the cyclically-arranged unit cells UR and UL is adjacent to any of the plurality of end cells at an endmost portion of arrangement cycle in each of the X direction and the Y direction, and regions having the plurality of end cells are different in an electric property from the unit cells UR and UL.