SiC Semiconductor Device with Checkered Pillar Configuration

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Solution Overview

Problem

Semiconductor devices with silicon carbide (SiC) substrates face challenges with stacking fault expansion, leading to forward-direction characteristic degradation (Vf degradation) due to basal plane dislocations, which affects the stability and electrical performance.

Innovation Solution

A semiconductor device design featuring a checkered configuration of p-type and n-type pillars along specific crystal directions, which suppresses the expansion of stacking faults by ensuring they stop at the bottom of p-type pillars, thereby preventing Vf degradation and maintaining stable characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional SiC semiconductor device structure is used, then manufacturing is simpler, but stacking faults expand from basal plane dislocations causing forward-direction characteristic degradation

Engineering Contradiction:
Improveelectrical performance stabilityVSAvoidsemiconductor member configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The semiconductor device is divided into multiple semiconductor members (first semiconductor member and second semiconductor member) with different conductivity types arranged in a checkered pattern. This segmentation prevents stacking fault expansion by creating boundaries that stop fault propagation, thereby improving electrical performance stability without excessive complexity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the semiconductor device are assigned different conductivity types (p-type and n-type) arranged in a checkered pattern. This local differentiation creates specific zones that suppress stacking fault expansion while maintaining overall device functionality, resolving the contradiction between reliability and complexity

Inventive Principle:
Principle #3Local quality

2Ease of manufacture

If stacking faults are allowed to expand, then device structure remains simple, but forward-direction characteristic degradation occurs

Engineering Contradiction:
Improvedevice structure simplicityVSAvoidstacking fault expansion
Core Design Contradiction:
Ease of manufactureVSObject-generated harmful factors

Solution Approach 1:

The invention converts the potentially harmful stacking faults into a controlled feature by using the alternating p-type and n-type semiconductor members as barriers. The faults are allowed to form but are stopped at the boundaries between differently typed semiconductor members, transforming a harmful uncontrolled expansion into a beneficial controlled feature that maintains device simplicity while preventing degradation

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

3Reliability

If semiconductor members are arranged in a checkered configuration to suppress stacking faults, then electrical performance stability improves, but manufacturing complexity increases

Engineering Contradiction:
Improveforward-direction characteristic stabilityVSAvoidsemiconductor member arrangement
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The device is segmented into first and second semiconductor members with different conductivity types arranged in a checkered pattern. This segmentation creates natural boundaries that suppress stacking fault expansion while maintaining manufacturability through systematic arrangement

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The checkered arrangement of p-type and n-type semiconductor members serves multiple functions: it suppresses stacking fault expansion, maintains electrical performance stability, and provides a systematic structure that can be manufactured using standard processes. This multi-functionality resolves the contradiction between reliability improvement and manufacturing complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11563090B2Semiconductor device
Publication Date: 2023.01.24 KK TOSHIBA
  • US11563090B2 patent drawing
  • US11563090B2 patent drawing
  • US11563090B2 patent drawing

AI summary

According to an embodiment of the invention, a semiconductor device includes a base body that includes silicon carbide, a first semiconductor member that includes silicon carbide and is of a first conductivity type, and a second semiconductor member that includes silicon carbide and is of a second conductivity type. A first direction from the base body toward the first semiconductor member is along a [0001] direction of the base body. The second semiconductor member includes a first region, a second region, and a third region. The first semiconductor member includes a fourth region. A second direction from the first region toward the second region is along a [1-100] direction of the base body. The fourth region is between the first region and the second region in the second direction. A third direction from the fourth region toward the third region is along a [11-20] direction of the base body.