SiC Semiconductor Device Orientation for Stacking Fault Resistance
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Solution Overview
Problem
Existing silicon carbide (SiC) semiconductor devices are prone to defects such as stacking faults, which can propagate and affect device performance, particularly in high-power applications, leading to increased on-state resistance and bipolar degradation.
Innovation Solution
The semiconductor device is oriented within the SiC crystal along an off-orientation direction, minimizing the impact of defects by aligning the first side longer than the second side, thereby reducing the propagation of stacking faults and improving stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If semiconductor devices are produced in SiC crystal, then high breakdown electric fields and high thermal conductivity are achieved, but the devices become vulnerable to stacking faults and defects
Solution Approach 1:
The patent applies asymmetry by orienting the semiconductor device structure asymmetrically within the SiC crystal lattice. Specifically, the device is configured with a preferred crystallographic orientation (e.g., <11-20> or <10-10> direction) that creates an asymmetric arrangement of atoms and bonds, which inherently resists the propagation of stacking faults by disrupting the regular stacking sequence that defects exploit.
Solution Approach 2:
The patent introduces a dimensional aspect by considering the three-dimensional crystallographic orientation of the device within the SiC lattice. By selecting specific orientation directions and angles in the crystal coordinate system, the device structure utilizes the third dimension (crystallographic orientation) to block defect propagation paths that would otherwise occur in conventional planar configurations.
2Reliability
If conventional semiconductor device configurations are used in SiC, then manufacturing simplicity is maintained, but device performance degrades due to defect propagation
Solution Approach 1:
The patent changes critical geometric parameters of the device configuration, specifically the crystallographic orientation angles and directional alignments within the SiC lattice. By optimizing parameters such as the orientation angle (e.g., 30 degrees from the normal to the substrate surface) and the alignment direction (<11-20> or <10-10>), the device achieves enhanced defect resistance while maintaining compatibility with standard fabrication processes.
Data Source
AI summary
In one general aspect, an apparatus can include a silicon carbide (SiC) crystal having a top surface aligned along a plane and the SiC crystal having an off-orientation direction. The apparatus including a semiconductor device defined within the SiC crystal. The semiconductor device having an outer perimeter where the outer perimeter has a first side aligned along the off-orientation direction and a second side aligned along a direction non-parallel to the off-orientation direction. The first side of the outer perimeter of the semiconductor device having a length longer than the second side of the outer perimeter of the semiconductor device.


