SiC Device Z1/2 Centers Suppress Stacking Faults
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Solution Overview
Problem
Conventional silicon carbide semiconductor devices face challenges in accurately controlling the thickness and impurity concentration of n-type epitaxial layers for effective recombination of minority carriers, leading to increased unit costs and inefficiencies in suppressing stacking faults due to high-temperature heat treatments that affect minority carrier lifetimes.
Innovation Solution
A silicon carbide semiconductor device with a pn junction structure featuring a Z1/2 center introduced through electron beam irradiation, reducing minority carrier lifetimes to 70 ns or less, and a trench gate structure that reduces hole density and suppresses stacking fault growth by controlling the impurity concentrations and epitaxial layer thicknesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-temperature heat treatment is applied to suppress stacking faults, then stacking fault suppression is improved, but minority carrier lifetime is reduced and manufacturing precision deteriorates
Solution Approach 1:
The patent changes the physical-chemical parameters of the drift region by introducing Z1/2 centers through electron beam irradiation, achieving stacking fault suppression without high-temperature heat treatment. This parameter change allows minority carrier lifetime to be maintained at 70ns or less while suppressing stacking faults, resolving the contradiction between reliability improvement and manufacturing precision deterioration
Solution Approach 2:
The patent replaces the thermal field (high-temperature heat treatment) with an electron beam field to achieve the same stacking fault suppression effect. By using electron beam irradiation to create Z1/2 centers, the process avoids the unwanted side effects of high-temperature treatment on minority carrier lifetime while maintaining stacking fault suppression
2Reliability
If n-type epitaxial layer thickness and impurity concentration are increased to enhance recombination, then minority carrier recombination is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent extracts the recombination enhancement function from the n-type epitaxial layer structure and relocates it to the drift region through Z1/2 center introduction. By placing the recombination centers directly in the drift region rather than relying on complex multi-layer epitaxial structures, the patent simplifies the overall device structure while maintaining effective minority carrier recombination
Solution Approach 2:
The patent changes the drift region properties by introducing Z1/2 centers, transforming it into an effective recombination region. This parameter change eliminates the need for complex n-type epitaxial layer thickness and impurity concentration control, simplifying manufacturing while achieving the desired recombination effect
3Reliability
If electron beam irradiation dose is increased to introduce more Z1/2 centers, then stacking fault suppression is improved, but ON resistance increases
Solution Approach 1:
The patent implements feedback control by measuring minority carrier lifetime and adjusting the electron beam irradiation dose accordingly. By targeting a specific minority carrier lifetime of 70ns or less, the process optimizes Z1/2 center concentration to achieve stacking fault suppression while controlling ON resistance, preventing excessive irradiation that would increase resistance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses stacking fault growth and reduces ON resistance while maintaining stable minority carrier lifetimes, enhancing the manufacturing ease and electrical characteristics of silicon carbide semiconductor devices.
Implementation Method 1
a Z1/2 center introduced through electron beam irradiation, reducing minority carrier lifetimes to 70 ns or less
Data Source
AI summary
A semiconductor device having a semiconductor substrate that includes first to third epitaxial layers provided sequentially on a starting substrate, the third epitaxial layer forming a pn junction with the second epitaxial layer, and including a plurality of first semiconductor regions formed on a second semiconductor region. The semiconductor device further includes a plurality of trenches penetrating the first and second semiconductor regions to reach the second epitaxial layer, a plurality of gate electrodes provided in the trenches respectively via a gate insulating film, a metal film in ohmic contact with the first semiconductor regions, a first electrode electrically connected to the first semiconductor regions via the metal film, and a second electrode provided at a back surface of the starting substrate. Each of the starting substrate and the first to third epitaxial layers contains silicon carbide. The silicon carbide semiconductor device has a vacancy trap in an entire area of the semiconductor substrate.