SiC Diode Leadframe Bonding with Cu/Ni/Sn Diffusion Soldering
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Solution Overview
Problem
There is a need for improved silicon carbide semiconductor devices with reduced lateral dimensions and enhanced current carrying capabilities to minimize overvoltages during switching operations, particularly for wide bandgap power devices like silicon carbide diodes.
Innovation Solution
A method involving a diode layer stack with a silicon carbide diode die, a copper layer, and a tin or indium containing layer, connected to a copper leadframe via a diffusion soldering process, forming an intermetallic compound layer comprising copper and tin, which enhances the bonding and current carrying capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional silicon-based power devices are used, then the device structure is simple and easy to manufacture, but the power density is limited and current carrying capability is insufficient
Solution Approach 1:
The patent changes the material parameter from silicon to silicon carbide, which fundamentally alters the electrical and thermal properties of the device. This material substitution enables higher power density and improved current carrying capability while maintaining device functionality. The copper/tin metallization stack further optimizes electrical parameters at the interface.
Solution Approach 2:
The patent employs a composite metallization structure consisting of multiple layers (copper, nickel, tin) with distinct functions. The copper layer provides electrical conductivity, the nickel layer provides adhesion and diffusion barrier, and the tin layer enables low-temperature soldering. This composite approach solves the contradiction by achieving high performance through material combination rather than single-material complexity.
2Power
If the lateral dimensions of silicon carbide devices are reduced, then the current carrying capability is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent changes the bonding process parameters by using diffusion soldering at relatively low temperatures (below 250°C) with the copper/tin metallization stack. This allows precise alignment and bonding of small lateral dimensions without requiring extreme manufacturing precision, as the low-temperature process reduces thermal stress and deformation.
Solution Approach 2:
The patent applies preliminary metallization processing to create the copper/tin layer stack on the silicon carbide device before bonding. This preliminary action prepares the surface with optimal bonding properties, enabling precise alignment and reliable connection even at reduced lateral dimensions, thereby reducing the actual manufacturing precision requirements during the bonding step.
3Reliability
If diffusion soldering with copper/tin metallization is used, then the bonding strength and current carrying capability are improved, but the manufacturing process complexity increases
Solution Approach 1:
The patent applies preliminary metallization processing to deposit the copper and tin layers on the silicon carbide device before the bonding step. This preliminary action prepares the surface with optimal bonding properties in advance, allowing the actual diffusion soldering process to proceed under relatively simple and controlled conditions, thereby reducing the overall manufacturing process complexity despite the enhanced bonding capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces lateral dimensions and improves current carrying capabilities of silicon carbide semiconductor devices, minimizing overvoltages and increasing the reliability of power semiconductor devices.
Implementation Method 1
performing a diffusion soldering process for connecting the diode layer stack with the layer stack to the first main surface of the die pad
Implementation Method 2
an intermetallic compound layer disposed between the die pad and the diode die, the intermetallic compound layer comprising copper and tin
Data Source
Figure 1~4
AI summary
A method (100) for fabricating a semiconductor device (20, 30) comprises: providing (110) a diode layer stack (10, 10A) comprising a silicon carbide diode die (11) comprising a first main surface at an anode side of the diode die (11) and a second main surface opposite to the first main surface at a cathode side of the diode die (11) and a layer stack (12) on the first main surface of the diode die (11), the layer stack (12) comprising a copper layer (12.1) disposed on the first main surface of the diode die (11) and a tin or indium containing layer (12.3) disposed above the copper layer (12.1); providing (120) a die pad (21) comprising a copper leadframe (21.1) comprising a first main surface and a second main surface opposite to the first main surface; and performing a diffusion soldering process (130) for connecting the diode layer stack (12) to the first main surface of the die pad (21), for example in a temperature range from 350°C to 400°C and/or for a time duration in a range from 50 ms to 1 s or from 100 ms to 200 ms, to form an intermetallic compound layer (12A) from the layer stack (12). The layer stack (12) may further comprise a nickel containing layer (12.2) disposed on the copper layer (12.1), wherein the tin containing layer (12.3) is disposed on the nickel containing layer (12.2). The copper leadframe (21.1) may further comprise nickel containing layers (21.2) disposed on both of the first and second main surfaces thereof. The nickel containing layer(s) (12.2, 21.2) may comprise pure nickel or an alloy of nickel with vanadium and/or phosphor. The tin or indium containing layer (12.3) may comprise pure tin or pure indium or an alloy of tin and gold or indium and gold. The diode layer stack (12) may further comprise a nickel layer (13) or a silver layer on the second surface of the diode die (11). The method may further comprise providing a lead (31) and connecting the nickel layer (13) or the silver layer of the diode die (11) by at least one of a bond wire, a wedge or a clip (32) with the lead (31). The intermetallic compound layer (12A) may comprise Cu and Sn or In, either in the form of a spatially homogeneous constitution or in the form of a structure in which two outer copper layers enclose an inner tin or indium layer. The intermetallic compound layer (12A) may comprise a layer structure comprising a symmetry around a central Sn or In layer. The intermetallic compound layer (12A) may further comprise nickel, wherein the intermetallic compound layer (12A) may comprise a layer sequence Cu/Ni/Sn/Ni/Cu or Cu/Ni/In/Ni/Cu, i.e., a layer sequence comprising a symmetry of the Cu and Ni layers around a central Sn or In layer.