SiC DMOSFET Source Structure for Higher Third-Quadrant Crossover Current
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Silicon carbide (SiC) power MOSFETs face reliability issues due to challenges in inversion-layer mobility and passivating dielectric layers, leading to performance and reliability problems, particularly in third quadrant cross over current.
Innovation Solution
A vertical Silicon Carbide double-implantation metal oxide semiconductor field-effect transistor (DMOSFET) design is implemented, featuring a first conductivity type second source region with a thickness and doping concentration optimized between the silicide layer and the second conductivity type well region, and a metal region with a target work function, to enhance turn-on voltage and reduce minority carrier injection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SiC power MOSFET design is used, then high blocking voltage is achieved, but third quadrant cross over current is limited and reliability issues occur
Solution Approach 1:
The patent introduces a second source region with different doping concentration and thickness characteristics between the silicide layer and the well region, creating local quality variations. This localized modification optimizes carrier injection characteristics specifically in the third quadrant operation mode without affecting other device regions, thereby improving reliability while controlling harmful minority carrier injection.
Solution Approach 2:
The patent optimizes the thickness and doping concentration parameters of the second source region to specific ranges. By changing these physical parameters within defined boundaries, the device achieves enhanced turn-on voltage characteristics and reduced minority carrier injection, directly addressing the reliability issue while maintaining high blocking voltage capability.
2Reliability
If source region thickness and doping are increased, then turn-on voltage is enhanced, but device complexity increases
Solution Approach 1:
The patent divides the source region into two distinct parts: a first source region and a second source region with different doping concentrations and thicknesses. This segmentation allows independent optimization of each region's characteristics, achieving stable turn-on voltage without requiring complex overall device restructuring. The segmented approach simplifies the manufacturing process compared to creating a completely new complex structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design increases third quadrant cross over current and improves device reliability by optimizing the source region thickness, doping concentration, and metal work function, thereby addressing performance and reliability issues in SiC power MOSFETs.
Implementation Method 1
the second source region is configured to deplete under reverse bias conditions to increase the turn-on voltage of the body diode
Implementation Method 2
forming a second conductivity type well region by performing a second conductivity type implantation
Data Source
AI summary
An embodiment relates to a n-type planar gate DMOSFET comprising a Silicon Carbide (SiC) substrate. The SiC substrate includes a N+ substrate, a N− drift layer, a P-well region and a first N+ source region within each P-well region. A second N+ source region is formed between the P-well region and a source metal via a silicide layer. During third quadrant operation of the DMOSFET, the second N+ source region starts depleting when a source terminal is positively biased with respect to a drain terminal. The second N+ source region impacts turn-on voltage of body diode regions of the DMOSFET by establishing short-circuitry between the P-well region and the source metal when the second N+ source region is completely depleted.