SiC Semiconductor Edge Termination Structure

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Solution Overview

Problem

Conventional silicon carbide semiconductor devices experience breakdown voltage degradation in the edge termination structure due to uneven electric field distribution and high current density, leading to avalanche breakdown, especially in the step-like portion with varying impurity concentrations and thicknesses.

Innovation Solution

A silicon carbide semiconductor device with a specific epitaxial layer structure and ion implantation technique to form p-type regions with controlled impurity concentrations and depths, creating a step-like portion and junction terminal extension (JTE) to distribute electric fields effectively and prevent breakdown voltage degradation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the edge termination structure is designed to maintain breakdown voltage, then the breakdown voltage should be high, but the electric fields concentrate in the edge termination structure causing breakdown voltage degradation

Engineering Contradiction:
Improvebreakdown voltageVSAvoidelectric field concentration
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies local quality by creating regions with different impurity concentrations in the edge termination structure. Specifically, it forms a first region with a first impurity concentration and a second region with a second impurity concentration that is lower than the first, adjacent to the first region. This gradual transition in impurity concentration distributes the electric field more evenly across the edge termination structure, preventing concentration at specific points and thereby maintaining high breakdown voltage without degradation.

Inventive Principle:
Principle #3Local quality

2Reliability

If ion implantation is used to form p-type regions with controlled impurity concentrations, then the breakdown voltage is improved, but the manufacturing process complexity increases

Engineering Contradiction:
Improvebreakdown voltageVSAvoidmanufacturing process
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by performing ion implantation to form the first and second p-type regions with controlled impurity concentrations during the manufacturing process. By pre-establishing these regions with specific impurity gradients before final device assembly, the patent ensures optimal electric field distribution and breakdown voltage characteristics are built into the structure, simplifying subsequent processing steps while achieving the desired reliability improvement.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively prevents breakdown voltage degradation in the edge termination structure, achieving higher avalanche tolerance and breakdown voltage, typically exceeding 1200 V, by ensuring the edge termination structure has a higher breakdown voltage than the active region.

Implementation Method 1

a method of manufacturing the silicon carbide semiconductor device by forming a plurality of first base regions, a first semiconductor region, a second semiconductor region, and a third semiconductor region

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS9905554B2Silicon carbide semiconductor device and method of manufacturing the same
Publication Date: 2018.02.27 FUJI ELECTRIC CO LTD
  • US9905554B2 patent drawing
  • US9905554B2 patent drawing
  • US9905554B2 patent drawing

AI summary

Provided are a silicon carbide semiconductor device that is capable of preventing breakdown voltage degradation in the edge termination structure and a method of manufacturing the same. The p-type regions 31, 32 and the p-type region 33, which serves as an electric field relaxation region and is connected to the first p-type base regions 10, are positioned under the step-like portion 40, and the bottom surfaces of the p-type regions 31, 32, 33 are substantially flatly connected to the bottom surface of the first p-type base regions 10. The first base regions have an impurity concentration of 4×1017 cm−3 or higher. The p-type region 33 is designed to have a lower impurity concentration than the first base regions 10 and higher than the p-type regions 31, 32. In this way, the breakdown voltage degradation in the edge termination structure 102 can be prevented.