SiC FET ESD Pulse Generator for Programmable High-Voltage Testing
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Solution Overview
Problem
Conventional electrostatic discharge (ESD) testing systems rely on hazardous mercury-wetted relays and semiconductor devices that are not fast enough to produce high pulse voltages, limiting their ability to generate variable and programmable ESD test pulses, and often result in leakage currents that can damage devices under test.
Innovation Solution
The use of a back-to-back connected pair of FETs, coupled with a test voltage source and opto-isolators, to produce bipolar test pulses of varying amplitudes and durations, eliminating the need for mercury-wetted relays and minimizing leakage currents, and allowing for configuration according to different ESD test models.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional mercury-wetted relays are used to produce ESD test pulses, then the required pulse voltages and shapes can be generated, but hazardous materials are used and the system becomes complex
Solution Approach 1:
The patent replaces the mechanical/electromagnetic relay system with a solid-state FET switching system. The FETs provide a purely electronic switching mechanism that eliminates mercury while maintaining the ability to generate high-voltage pulses through capacitor discharge through the semiconductor switches.
Solution Approach 2:
The patent extracts and removes the hazardous relay component from the ESD test system, replacing it with a solid-state FET-based switching circuit that achieves the same functional requirements without the harmful materials.
2Device complexity
If conventional semiconductor devices are used for ESD testing, then the system is simpler, but the devices are not fast enough to produce high pulse voltages
Solution Approach 1:
The patent changes the key parameter of switching speed by using SiC FETs with rise times of 1-10 ns, which are significantly faster than conventional semiconductor devices. This parameter change enables the system to generate high-voltage pulses at the required speeds for ESD testing while maintaining solid-state simplicity.
3Speed
If avalanche transistors are used to produce fast pulses, then the switching speed is sufficient, but the voltage is fixed and not programmable
Solution Approach 1:
The patent introduces dynamic programmability by using FETs with controlled gate voltages that can be adjusted to create different discharge currents. This allows the same fast-switching architecture to produce variable pulse amplitudes and shapes by changing the gate control parameters, making the system adaptable to different ESD test models.
4Device complexity
If conventional semiconductor switches are used, then the system is simpler, but leakage currents can destroy the device under test
Solution Approach 1:
The patent applies local quality by using SiC FETs with specifically engineered low-leakage characteristics in the critical switching positions. The material selection and device design focus on minimizing leakage current at the switching junctions while maintaining the overall simplicity of the solid-state architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables the production of high-voltage ESD test pulses with low aberrations, compliant with industry standards, and prevents damage to devices under test by eliminating leakage currents, while being cost-effective and adaptable to various ESD test modes.
Implementation Method 1
An ESD test capacitor is situated to be charged by the test voltage source and discharged through a device under test (DUT) and the first FET and a second FET to produce a test pulse
Implementation Method 2
first and second opto-isolators are coupled to respective gates of the first FET and the second FET and to receive the control pulse from a pulse generator
Data Source
AI summary
Electrostatic discharge (ESD) test systems include a FET-based pulse generator using pairs of back-to-back FETs coupled to produce an ESD pulse based on discharging a capacitor that is coupled in series with a device under test (DUT). A number of FETs can be selected based on an intended ESD test voltage magnitude.