SiC Gate Pad Layout for ESD-Robust Field Oxide Removal
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Solution Overview
Problem
Conventional silicon carbide semiconductor devices face challenges with electric field concentration and reduced electrostatic discharge (ESD) capability when the field oxide film is removed, leading to potential destruction of the gate electrode pad during ESD tests.
Innovation Solution
The silicon carbide semiconductor device design omits p++-type contact regions in specific regions of the gate pad portion and corner portions, using a high-temperature oxide film in contact with the p-type base layer to maintain ESD capability without the field oxide film, thereby reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the field oxide film is removed to reduce manufacturing complexity, then manufacturing cost is reduced, but electric field concentration occurs and ESD capability deteriorates
Solution Approach 1:
The patent applies local quality by creating regions with different impurity concentrations within the semiconductor layer. Specifically, a first region with a first impurity concentration and a second region with a second impurity concentration (different from the first) are formed in specific areas of the gate pad portion. This local variation in impurity concentration allows the structure to maintain ESD capability without requiring the field oxide film, thereby reducing manufacturing complexity while preserving reliability.
2Ease of manufacture
If the field oxide film is removed to simplify manufacturing, then manufacturing cost is reduced, but potential destruction of gate electrode pad occurs during ESD tests
Solution Approach 1:
The patent implements local quality by forming regions with specifically controlled impurity concentrations in the gate pad portion. The first region with a first impurity concentration and the second region with a second impurity concentration are strategically positioned to manage electric field distribution. This local modification eliminates the need for the field oxide film, simplifying manufacturing and reducing costs, while simultaneously preventing electric field concentration that would otherwise cause gate electrode pad destruction during ESD tests.
3Productivity
If p++-type contact regions are omitted in specific regions, then manufacturing steps are reduced, but electric field management becomes more challenging
Solution Approach 1:
The patent applies local quality by creating regions with different impurity concentrations (first impurity concentration in the first region, second impurity concentration in the second region) in specific areas of the gate pad portion. This localized control of electrical properties enables effective electric field management without requiring p++-type contact regions in all areas, thereby reducing manufacturing steps while maintaining proper electric field distribution.
Data Source
AI summary
A silicon carbide semiconductor device has a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, second semiconductor regions of the second conductivity type, a gate insulating film, gate electrodes, first electrodes, a second electrode, and a gate pad portion configured by a gate electrode pad and a connecting portion. The second semiconductor layer includes a first region facing the connecting portion and a second region facing a corner portion of the gate electrode pad, and the first and second regions are free of the second semiconductor regions. The oxide film is provided on surfaces of the second semiconductor regions and the first and second regions, and the oxide film and the gate insulating film are made of a same material.