SiC Gate Trench Rounding to Prevent MOSFET Gate Oxide Breakdown
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Power MOSFETs face a significant challenge due to the breakdown of the gate oxide layer, which is exacerbated by high electric fields during device operation, leading to defects and eventual short-circuit failure.
Innovation Solution
The design incorporates a silicon carbide based semiconductor layer structure with gate trenches having rounded lower and upper corners, where the radius of curvature of the lower corners exceeds that of the upper corners, and the gate electrode is recessed to be below the upper surface of the semiconductor layer structure, thereby reducing peak electric field values in the gate dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the gate electrode is insulated from the channel region by a thin gate oxide layer, then minimal gate current is required to maintain the MOSFET in its on-state, but the gate oxide layer is susceptible to breakdown under high electric fields
Solution Approach 1:
The patent applies curvature by rounding the upper corners of the gate trench instead of leaving them sharp. This spherical/curved geometry distributes the electric field more uniformly across the gate oxide layer, eliminating the concentrated high electric field regions at sharp corners that cause breakdown. The rounded corners maintain the thin gate oxide structure for low gate current while preventing the reliability issue of oxide breakdown.
2Ease of manufacture
If the gate trench corners are left sharp, then the manufacturing process is simpler, but electric field crowding occurs at the corners leading to increased breakdown risk
Solution Approach 1:
The patent introduces curvature at the gate trench upper corners to eliminate electric field crowding. This is achieved through a multi-step etching process with selective masking that rounds the corners during fabrication. While this adds some manufacturing complexity, it significantly improves reliability by distributing the electric field uniformly, preventing the concentration effects that occur at sharp corners.
Solution Approach 2:
The patent applies local quality by selectively rounding only the upper corners of the gate trench while maintaining the rest of the trench structure. This localized modification targets specifically the region where electric field crowding occurs (at the upper corners near the gate electrode) without altering other parts of the device, thus improving reliability where needed while minimizing impact on manufacturing complexity.
3Device complexity
If the gate electrode upper surface is flush with or above the semiconductor layer structure surface, then the device structure is simpler, but peak electric field values in the gate dielectric layer increase
Solution Approach 1:
The patent combines curvature of the gate trench upper corners with recessing the gate electrode surface to eliminate peak electric fields in the gate dielectric. The curved trench geometry and recessed electrode work together to distribute the electric field uniformly, preventing concentration at the interface between the gate electrode and semiconductor layer structure.
Solution Approach 2:
The patent applies asymmetry by making the gate electrode upper surface non-planar relative to the semiconductor layer structure. The gate electrode is recessed below the surface level, creating an asymmetric structure that eliminates the sharp interface that would concentrate electric fields. This asymmetric design improves reliability by distributing electric field stress more evenly across the gate dielectric layer.
Data Source
AI summary
A semiconductor device comprises a silicon carbide based semiconductor layer structure that comprises an active region. A gate trench is provided in an upper portion of the semiconductor layer structure, the gate trench having a first rounded lower corner and a second rounded lower corner. A gate electrode is provided in the gate trench. Within the active region, an upper surface of the gate electrode is below or coplanar with an upper surface of the semiconductor layer structure.