SiC Hetero Junction Device With Triple Contact Point
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing silicon carbide semiconductor devices face challenges in achieving high voltage capability and low on-resistance due to restrictive field relaxing effects, which lead to increased on-resistance and current leakage.
Innovation Solution
A semiconductor device structure featuring a hetero junction with a triple contact point, including a P-type field relaxing region connected to the source electrode, allows for effective field relaxation and inversion layer formation, reducing on-resistance and enhancing high voltage capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a P type region is formed on the gate electrode and on a silicon carbide SiC region below the gate electrode to relax the field, then the gate insulating film is protected, but the field relaxing effect is restrictive and on-resistance increases
Solution Approach 1:
The patent applies local quality by forming a P-type field relaxing region with specific impurity concentration (1×10^16 to 1×10^18 atoms/cm³) in a localized area beneath the gate electrode, rather than uniformly throughout the device. This localized doping creates an inversion layer precisely where needed to relax the electric field at the gate insulating film interface, while maintaining low resistance in other critical current paths. The selective placement and controlled doping concentration enable differentiated functionality within the semiconductor structure.
2Reliability
If the P type region is formed in a position sufficiently adjacent to the drive point, then field relaxing is implemented when the element is off, but the current passage is narrowed when the element is on, increasing on-resistance
Solution Approach 1:
The patent resolves this contradiction by carefully controlling the impurity concentration parameter of the P-type field relaxing region, specifying it should be in the range of 1×10^16 to 1×10^18 atoms/cm³. This parameter optimization allows the region to form an inversion layer for effective field relaxation in the off-state, while the controlled concentration prevents excessive depletion region expansion that would narrow the current passage in the on-state. The gate voltage parameter is also utilized to dynamically control the inversion layer formation, enabling state-dependent functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure effectively relaxes the field when the device is off, while forming an inversion layer when on, thereby improving the trade-off between off-state protection and on-state current passage, achieving high reverse blocking voltage and low on-resistance.
Implementation Method 1
a first face of the second conductivity-semiconductor region is configured to have such an impurity concentration that allows a field from the gate electrode to form an inversion layer on the first face of the second conductivity-semiconductor region
Implementation Method 2
a voltage applied to a gate electrode controls thickness of a barrier at the hetero interface, and a tunnel current allows a carrier to pass by
Implementation Method 3
a P type region is formed on the gate electrode and on a silicon carbide SiC region below the gate electrode, thereby relaxing a field applied to a gate insulating film
Data Source
AI summary
A semiconductor device, includes: a first conductivity-semiconductor substrate; a hetero semiconductor region for forming a hetero junction with the first conductivity-semiconductor substrate; a gate electrode adjacent to a part of the hetero junction by way of a gate insulating film; a drain electrode connecting to the first conductivity-semiconductor substrate; a source electrode connecting to the hetero semiconductor region; and a second conductivity-semiconductor region formed on a part of a first face of the first conductivity-semiconductor substrate in such a configuration as to oppose the gate electrode via the gate insulating film, the gate insulating film, the hetero semiconductor region and the first conductivity-semiconductor substrate contacting each other to thereby form a triple contact point. A first face of the second conductivity-semiconductor region has such an impurity concentration that allows a field from the gate electrode to form an inversion layer on the first face of the second conductivity-semiconductor region.