SiC MOSFET Cell Layout for Lower Leakage and Gate Capacitance
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Solution Overview
Problem
Conventional silicon carbide metal-oxide-semiconductor field-effect transistor (SiC MOSFET) devices integrated with Schottky diodes face issues such as large current leakage, low breakdown voltage, and increased gate electrode capacitance, which affect their performance in high-frequency and high-power applications.
Innovation Solution
The silicon carbide metal-oxide-semiconductor field-effect transistor (SiC MOSFET) device is designed with a substrate and epitaxy layer, featuring cell units with specific conductivity types and structures that include Schottky regions, junction field effect regions, well regions, and gate structures, allowing for reduced forward bias voltage, decreased gate electrode capacitance, and enhanced current density through optimized cell configurations and implantation sections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If Schottky contact metals are located in central positions of junction field effect regions, then gate electrode capacitance is reduced, but current leakage increases and breakdown voltage decreases
Solution Approach 1:
The patent employs asymmetric cell structures where first cells and second cells have different configurations. Specifically, Schottky contact metals in first cells are positioned differently compared to those in second cells, creating non-uniform electric field distributions that simultaneously reduce gate capacitance and maintain breakdown voltage through complementary arrangements.
Solution Approach 2:
Different regions of the device are given different properties: first cells have Schottky contacts optimized for one function while second cells have Schottky contacts optimized for another function. This local differentiation allows the device to achieve multiple performance targets simultaneously by optimizing each region for its specific role.
2Reliability
If Schottky contact electrodes are located between adjacent ohmic contact metals, then forward and reverse currents flow through different pathways, but cell size increases
Solution Approach 1:
The patent merges the functions of first cells and second cells into a single integrated device structure. By combining complementary cell types in an alternating pattern, the device achieves separate current pathways for forward and reverse currents while maintaining a compact overall footprint that is smaller than using only one cell type.
Solution Approach 2:
The patent arranges first cells and second cells in an alternating spatial pattern, utilizing two-dimensional layout optimization. This dimensional arrangement allows current pathways to be separated in the planar direction while maintaining vertical integration, thereby reducing the effective cell size compared to linear arrangements.
3Device complexity
If gate electrodes cover entire junction field effect transistor regions, then device structure is simplified, but gate electrode capacitance increases and current density decreases
Solution Approach 1:
The gate electrode structure is segmented into different regions corresponding to first cells and second cells. Rather than a single continuous gate covering the entire junction field effect region, the gate is divided into discrete segments that align with individual cell boundaries, allowing independent optimization of each segment and reducing total gate capacitance while maintaining structural simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in reduced current leakage, increased breakdown voltage, and improved current density, making the SiC MOSFET device more suitable for high-frequency and high-power applications while minimizing device size.
Implementation Method 1
metal-oxide-semiconductor field-effect transistor
Implementation Method 2
Schottky contact metals, Schottky regions, Schottky diodes
Data Source
AI summary
A silicon carbide metal oxide semiconductor field effect transistor device includes a substrate, an epitaxial layer, and a plurality of cell units each of which includes a first cell and a second cell that are disposed in the epitaxy layer and connected to each other in the epitaxy layer. The first cell includes a first Schottky region, a first junction field effect region, a first well region, a first well contact structure, a first source region, a first Schottky metal, a first ohmic contact metal, and a first gate structure. The second cell includes a second Schottky region, a second junction field effect region, a second well region, a second well contact structure, a second source region, a second Schottky metal, a second ohmic contact metal, and a second gate structure. In the epitaxial layer, the first junction field effect region is connected to the second Schottky region.