SiC Vertical MOSFET Channel Optimization
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Solution Overview
Problem
Existing semiconductor devices with silicon carbide (SiC) vertical MOSFETs face challenges in minimizing on-state resistance while maintaining breakdown voltage, as methods to reduce on-state resistance often lead to decreased breakdown voltage and difficulties in suppressing spreading resistance in the JFET region.
Innovation Solution
A semiconductor device structure featuring a drain region with an epitaxial layer of lower impurity concentration, selectively buried base regions, and higher impurity concentration semiconductor regions to optimize channel formation and reduce on-state resistance, while maintaining breakdown voltage through specific depth and impurity concentration profiles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a p-type region is deposited on the n-type drift region and p+-type base region is buried, then on-state resistance is minimized, but the formation of n-type region below the p+-type base region is hindered
Solution Approach 1:
The patent applies preliminary action by forming the first n-type semiconductor region with higher impurity concentration at a deeper position before forming the p-type base region. This preliminary formation of the deep n-type region ensures that subsequent p-type base region formation does not hinder the existence of the n-type region, as it was already established at a greater depth. This sequence of operations resolves the manufacturing difficulty while maintaining low on-state resistance.
Solution Approach 2:
The patent resolves the conflict by transitioning to a three-dimensional spatial arrangement where the first n-type semiconductor region is positioned at a greater depth than the p-type base region. This vertical dimensionality separation allows both the p-type base region and deep n-type region to coexist without interference, enabling both low on-state resistance and ease of manufacture.
2Loss of energy
If the impurity concentration is increased to reduce on-state resistance, then switching loss is reduced, but spreading resistance in the JFET region increases
Solution Approach 1:
The patent applies local quality by creating a first n-type semiconductor region with higher impurity concentration specifically at a deeper position to reduce on-state resistance and switching loss, while the second n-type semiconductor region with lower impurity concentration is positioned at a shallower position to maintain low spreading resistance in the JFET region. This localized differentiation resolves the contradiction between reducing switching loss and preventing spreading resistance increase.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure effectively decreases on-state resistance while protecting breakdown voltage by optimizing the depth and impurity concentration of semiconductor regions, preventing depletion and spreading resistance, thus enhancing the semiconductor device's performance.
Implementation Method 1
an epitaxial layer of the first conductivity-type, provided on a top surface of the drain region
Data Source
AI summary
A semiconductor device includes: an n+-type drain region made of a wide-bandgap semiconductor material; an n-type epitaxial layer provided on the top surface of the drain region; an n-type first semiconductor region provided at an upper portion of the epitaxial layer and having a higher impurity concentration than the epitaxial layer; an n-type second semiconductor region provided on the first semiconductor region and having a higher impurity concentration than the first semiconductor region; p-type base regions surrounding to include an upper portion in the middle of the second semiconductor region; n-type source regions provided at upper portions of the base regions to form a channel; and a gate electrode which controls a surface potentials of the channels.