SiC MOSFET Channel Self-Alignment for Lower On-Resistance

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Solution Overview

Problem

Existing silicon carbide (SiC) MOSFET devices face challenges in precisely controlling the channel length due to alignment deviations in non-self-alignment processes, which affect performance and reliability, and conventional methods struggle to further reduce on-resistance.

Innovation Solution

A self-aligned manufacturing method for SiC MOSFETs that adjusts ion implantation angle and energy to form a body region, using a barrier layer to control the transverse extension length of the channel, allowing for a shorter channel and reduced on-resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If non-self-alignment process with two independent masks is used to form channel, then ion implantation can be performed to form P-type body region and N+ source region, but alignment deviation between different photoetching processes affects manufacturing precision and device reliability

Engineering Contradiction:
Improvedevice reliabilityVSAvoidalignment precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent merges the formation of P-type body region and N+ source region into a single ion implantation process step. By using one mask patterned with both body and source regions, the patent eliminates the alignment deviation between multiple photoetching processes, thereby improving manufacturing precision while maintaining device reliability.

Inventive Principle:
Principle #5Merging (Combining)

2Loss of energy

If channel length is reduced to lower on-resistance, then device performance improves, but conventional self-alignment methods using oxidized polysilicon cannot precisely control channel length

Engineering Contradiction:
Improveon-resistanceVSAvoidchannel length control precision
Core Design Contradiction:
Loss of energyVSManufacturing precision

Solution Approach 1:

The patent changes the controlling parameter for channel length from oxidized polysilicon thickness to the physical mask pattern dimensions. By defining the source region boundary directly in the mask pattern, the channel length becomes precisely controllable through photolithography parameters rather than being limited by oxidation process variability, enabling shorter channels with precise control.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If conventional self-alignment method using oxidized polysilicon barrier layer is used, then N+ source region can be formed with self-alignment, but channel length cannot be precisely controlled and on-resistance cannot be further reduced

Engineering Contradiction:
Improveself-alignment reliabilityVSAvoidchannel length precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent extracts and removes the oxidized polysilicon barrier layer formation step from the conventional self-alignment process. Instead of relying on polysilicon oxidation to define the source region boundary, the patent directly patterns the source region in the mask, eliminating the intermediate oxidation step and its associated variability in channel length control.

Inventive Principle:
Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method enables precise control of the channel length to less than 0.5 μm, improving device reliability and reducing on-resistance, while maintaining high performance.

Implementation Method 1

performing an ion implantation process on the epitaxial layer to form a body region of a second doping type

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS12538723B2Silicon carbide MOSFET device and manufacturing method thereof
Publication Date: 2026.01.27 HANGZHOU SILICON-MAGIC SEMICON TECH CO LTD
  • US12538723B2 patent drawing
  • US12538723B2 patent drawing
  • US12538723B2 patent drawing

AI summary

Disclosed is a silicon carbide MOSFET device and a manufacturing method thereof. The manufacturing method comprises: forming a source region in an epitaxial layer; forming a body region in the epitaxial layer; forming a gate structure, comprising a gate dielectric layer, a gate conductor layer and an interlayer dielectric layer; forming an opening in the interlayer dielectric layer to expose the source region; forming a source contact connected to the source region via the opening, wherein an ion implantation angle of the ion implantation process is controlled to make a transverse extension range of the body region larger than a transverse extension range of the source region, so that a channel that extends transversely is formed by a portion, which is peripheral to the source region, of the body region, and at least a portion of the gate conductor layer is located above the channel.