SiC MOSFET Corner Region Design for Parasitic Transistor Suppression
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional vertical metal oxide semiconductor field effect transistors (MOSFETs) using silicon carbide face issues with parasitic transistor operation due to high electric field concentrations at corner portions, leading to potential element destruction during high voltage operations.
Innovation Solution
The semiconductor device incorporates a structure with specific impurity concentration and thickness gradients in silicon carbide layers, including a p+-type contact region thicker than the n+-type source region and a narrower width facing the p-type base region, which reduces electric field concentration and prevents parasitic transistor operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If breakdown occurs in the active region with larger area, then the vertical MOSFET increases tolerance by reducing absorption energy per unit area, but high electric field concentration at corner portions of the base region causes parasitic transistor operation leading to element destruction
Solution Approach 1:
The patent applies local quality by creating an n-type region with higher impurity concentration specifically at the corner portion of the base region, while maintaining lower impurity concentration in other areas. This localized modification suppresses parasitic transistor operation at the critical corner region without affecting the overall breakdown characteristics of the active region, thereby resolving the contradiction between improving tolerance and preventing parasitic transistor operation.
Solution Approach 2:
The patent changes the impurity concentration parameter locally at the corner portion of the base region by forming an n-type region with higher impurity concentration. This parameter change modifies the electrical characteristics at the critical location, preventing parasitic transistor turn-on while maintaining the desired breakdown behavior in the active region, thus resolving the technical contradiction.
2Reliability
If a region with high oxygen concentration is provided in the base region to block base current, then parasitic transistor operation is suppressed, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
Instead of introducing a completely new structure with high oxygen concentration regions, the patent achieves parasitic transistor suppression by changing the impurity concentration parameter - specifically by forming an n-type region with higher dopant concentration at the corner portion of the base region. This approach suppresses parasitic transistor operation while maintaining a relatively simple device structure and manufacturing process, thus resolving the contradiction between reliability improvement and device complexity.
3Reliability
If an n+-type region is formed apart from the p-type base region below the contact region, then parasitic transistor operation is suppressed and tolerance is improved, but the device complexity increases
Solution Approach 1:
The patent merges the function of the n-type region into the base region structure itself, rather than creating a separate n+-type region as in conventional designs. By forming an n-type region with higher impurity concentration at the corner portion of the base region, the patent combines the base region and the parasitic transistor suppression function into a single integrated structure, thereby reducing device complexity while maintaining improved tolerance and parasitic transistor suppression.
Data Source
AI summary
A semiconductor device includes a silicon carbide semiconductor substrate, a first silicon carbide layer of a first conductivity type, a first semiconductor region of a second conductivity type, a second semiconductor region of the first conductivity type, a third semiconductor region of the second conductivity type, a gate insulating film, a gate electrode, an interlayer insulating film, a source electrode, and a drain electrode. The third semiconductor region is thicker than the second semiconductor region and a width of a side of the third semiconductor region facing the first semiconductor region is narrower than a width of a side thereof facing the source electrode.