SiC Vertical MOSFET Double Trench Gate Reliability
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Solution Overview
Problem
Existing semiconductor devices face challenges in reducing on-resistance and improving reliability, particularly in high-temperature applications, due to limitations in channel area per unit area and electric field management in trench gate structures.
Innovation Solution
A silicon carbide-based vertical MOSFET with a double trench structure and specific impurity concentration profiles, including a gate trench bottom region and field limiting region, is designed to increase channel area and limit electric fields, reducing on-resistance and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a trench gate structure is applied to increase channel area per unit area, then on-resistance is reduced, but electric field management becomes more difficult and reliability deteriorates
Solution Approach 1:
The patent applies local quality by creating a field limiting region with specific p-type impurity concentration (1×10^16 to 1×10^18 atoms/cm³) localized at the trench bottom, while maintaining different impurity concentrations in other regions. This localized modification of material properties allows the trench gate structure to achieve both high channel area for low on-resistance and controlled electric field distribution for improved reliability, resolving the contradiction between these two requirements
2Reliability
If impurity concentration in the drift region is increased to improve conductivity, then on-resistance is reduced, but breakdown voltage decreases and reliability worsens
Solution Approach 1:
The patent utilizes parameter changes by precisely controlling the impurity concentration distribution across different regions: the drift region maintains low impurity concentration (1×10^14 to 1×10^16 atoms/cm³) to ensure high breakdown voltage, while the field limiting region has intermediate concentration (1×10^16 to 1×10^18 atoms/cm³) to manage electric fields, and the source region has high concentration (1×10^18 to 1×10^20 atoms/cm³) for low contact resistance. This multi-parameter optimization resolves the contradiction between breakdown voltage and on-resistance
3Reliability
If channel area is increased to reduce on-resistance, then device area must be increased, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent applies dimensionality change by transitioning from a planar gate structure to a three-dimensional trench gate structure that extends vertically into the semiconductor substrate. This vertical dimension allows the channel area to be increased without proportionally increasing the device footprint, as the channel area is now determined by the trench perimeter and depth rather than just the surface area. The field limiting region at the trench bottom further optimizes this three-dimensional structure to manage electric fields effectively
Data Source
AI summary
A semiconductor device of an embodiment includes a silicon carbide layer having a first plane and a second plane and includes a trench located on a first plane side and has a first region and a second region, a first silicon carbide region of an n-type, a second silicon carbide region of a p-type between the first silicon carbide region and the first plane, a third silicon carbide region of the n-type between the second silicon carbide region and the first plane, and a fourth silicon carbide region of the p-type between the second region and the first silicon carbide region; a gate electrode in the first region; a first electrode on the first plane side of the silicon carbide layer, a part of the first electrode is located in the second region and is in contact with the third and the fourth silicon carbide region; and a second electrode.