SiC MOSFET Gate-Open Failure Detection Circuit
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Solution Overview
Problem
Silicon Carbide (SiC) power MOSFETs face reliability challenges due to intermittent gate-open failures caused by bond-wire cracking or liftoff, which are difficult to detect and can lead to incorrect lifetime estimation and potential shoot-through events during DC power cycling tests.
Innovation Solution
A robust on-board detection system using a detection circuit with comparators and logic circuits to measure drain-source and gate voltages, capable of detecting gate-open failures in as low as 150 ns, and preventing shoot-through events by identifying conduction and open faults in real-time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DC power cycling tests are used to accelerate package related aging mechanisms, then device reliability testing is improved, but gate-open failures become difficult to detect and may lead to incorrect lifetime estimation
Solution Approach 1:
The patent applies preliminary action by implementing a detection circuit that continuously monitors gate voltage and drain-source voltage before catastrophic failures occur. The circuit detects gate-open conditions early in the aging process by comparing voltages against threshold values, enabling proactive identification of bond-wire degradation before it leads to device failure or incorrect lifetime estimation.
Solution Approach 2:
The patent implements feedback through a detection circuit that continuously monitors device parameters (gate voltage, drain-source voltage) and provides real-time feedback on device health status. The circuit compares measured voltages against predetermined thresholds and generates feedback signals indicating normal operation, gate-open conditions, or other failure modes, enabling continuous assessment of device reliability during power cycling tests.
2Duration of action of stationary object
If gate-open failures are not detected, then device operation continues, but shoot-through events may occur causing catastrophic failure
Solution Approach 1:
The patent applies preliminary anti-action by implementing a detection circuit that identifies gate-open failures before they can cause shoot-through events. The circuit continuously monitors gate and drain-source voltages, compares them against safety thresholds, and generates early warning signals that enable protective actions to be taken before catastrophic failure occurs, thereby preventing harmful shoot-through events.
Solution Approach 2:
The patent implements feedback through continuous monitoring of device parameters and real-time generation of fault detection signals. The detection circuit provides feedback on device health status, enabling immediate protective actions when gate-open conditions are detected, thus preventing the progression to shoot-through events and catastrophic failure while maintaining operational safety.
3Reliability
If conventional protection techniques are used, then basic device protection is provided, but third quadrant operation faults remain undetected
Solution Approach 1:
The patent applies universality by designing a detection circuit that provides comprehensive fault detection across all four operation quadrants of the SiC MOSFET. The circuit monitors gate voltage and drain-source voltage simultaneously and uses threshold comparison logic that is effective regardless of the operating quadrant, enabling unified protection for forward conduction, reverse conduction, forward blocking, and reverse blocking operations.
Solution Approach 2:
The patent implements parameter changes by using dual voltage parameter monitoring (gate voltage and drain-source voltage) with dynamically applicable threshold values. The detection circuit compares measured parameters against predetermined thresholds that account for different operating conditions and quadrants, enabling accurate fault detection across the full range of device operation modes including third quadrant reverse conduction.
Data Source
AI summary
A system to detect gate-open failures in a MOS based insulated gate transistor can include a detection circuit, including a first circuit configured to measure a drain-source voltage across the MOS based insulated gate transistor, a first comparator circuit can be configured to compare the measured drain-source voltage to a threshold drain-source conduction voltage indicating a conduction state of a channel of the MOS based insulated gate transistor, a second circuit can be configured to measure a gate voltage applied at a gate of the MOS-based insulated gate transistor, a second comparator circuit can be configured to compare the gate voltage applied at the gate to a threshold gate voltage for the MOS based insulated gate transistor to provide an indication of whether the gate voltage applied at the gate is sufficient to activate conduction in the channel and a logic circuit can be configured to detect a gate-open failure of the MOS based insulated gate transistor based on the conduction state of the channel and the indication of whether the gate voltage applied at the gate is sufficient to activate conduction in the channel when the MOS based insulated gate transistor is in an on state or an off state.