SiC Trench MOSFET p+ Stopper Regions Leakage Control
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Solution Overview
Problem
The challenge in semiconductor devices is to reduce channel leakage current while minimizing on-state resistance, particularly in trench gate type MOSFETs, as shortening the channel length increases undesirable leakage currents when the MOSFET is turned off.
Innovation Solution
The semiconductor device incorporates a silicon carbide layer with specific conductivity type regions and trenches, including p+ type stopper regions with higher impurity concentrations, strategically positioned to reduce channel leakage by preventing depletion layer extension and maintaining surface potential, along with optimized impurity concentrations and depths to manage channel resistance and electric field concentration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the channel length is decreased to reduce on-state resistance, then on-state resistance is reduced, but channel leakage current increases
Solution Approach 1:
The patent applies local quality by creating regions with different impurity concentrations within the semiconductor structure. Specifically, it introduces a first region with a first conductivity type and a second region with a second conductivity type, where the impurity concentration varies locally to control electric field distribution and prevent depletion layer extension into the channel, thereby reducing leakage current while maintaining low on-state resistance.
Solution Approach 2:
The patent changes physical parameters by introducing regions with different conductivity types and impurity concentrations. The first region has a first conductivity type with a specific impurity concentration, while the second region has a second conductivity type with a different impurity concentration, allowing optimization of both on-state resistance and leakage current characteristics through parameter variation.
2Object-generated harmful factors
If p+ type stopper regions with higher impurity concentrations are introduced to reduce channel leakage, then channel leakage is reduced, but device complexity increases
Solution Approach 1:
The patent segments the semiconductor structure into distinct functional regions: a first region with a first conductivity type, a second region with a second conductivity type, and p+ type stopper regions with higher impurity concentrations. This segmentation allows each region to perform its specific function in controlling electric field distribution and preventing depletion layer extension, thereby reducing channel leakage current.
Solution Approach 2:
The p+ type stopper regions act as intermediary elements between the first and second regions. These stopper regions with higher impurity concentrations serve as mediators to control the electric field distribution and prevent the depletion layer from extending into the channel, effectively reducing channel leakage current while maintaining a manageable structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces channel leakage currents, enhances breakdown voltage, and improves the reliability of the MOSFET by controlling surface potential and electric field distribution, thereby achieving lower on-state resistance and increased avalanche resistance.
Implementation Method 1
p+ type stopper regions with higher impurity concentrations, strategically positioned to reduce channel leakage by preventing depletion layer extension and maintaining surface potential
Implementation Method 2
optimized impurity concentrations and depths to manage channel resistance and electric field concentration
Data Source
AI summary
A device includes a silicon carbide layer between first and second electrodes. The silicon carbide layer includes first region, second region between the first region and second electrode, and third region between the second region and second electrode. The device includes first and second trenches, through the second and third regions and terminating within the first region, having a layer formed thereon, and spaced by portions of the second and third regions. The silicon carbide layer includes fourth region between the third region and first trench, and fifth region between the third region and second trench. The second region includes a fourth portion between first and second portions, and a fifth portion between second and third portions. The first, second, and third portions have lower impurity than the fourth and fifth portions, and the fourth and fifth portions extend closer to the first electrode than do the other portions.


