SiC MOSFET Trench Structure with Segmented Base Regions
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Solution Overview
Problem
Conventional silicon carbide MOSFETs with trench structures face increased resistance and reduced efficiency when attempting to reduce cell pitch, leading to degraded stability in low current regions and hindered power conversion efficiency.
Innovation Solution
The semiconductor device configuration includes multiple MOS cells between body diode cells, with second p+-type base regions disposed apart from first p+-type base regions, increasing the number of trench sidewalls per unit length and reducing ON resistance, while maintaining reliability by preventing high electric field application during avalanche breakdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cell pitch is reduced to increase unit cell density, then device element ON resistance decreases, but resistance in low current regions increases and stability degrades
Solution Approach 1:
The device structure is segmented into alternating first regions (with first p+-type base regions) and second regions (with second p+-type base regions). This segmentation allows different regions to serve different functions: first regions provide stable electrical characteristics in low current conditions, while second regions enable reduced cell pitch and lower ON resistance. The segmentation resolves the contradiction by spatially separating the requirements for stability and density.
Solution Approach 2:
Different regions of the semiconductor device are given different local qualities through selective provision of first and second p+-type base regions. The first p+-type base regions are optimized for stability in low current regions, while the second p+-type base regions are optimized for reducing ON resistance and enabling reduced cell pitch. This local differentiation allows each region to perform its specific function optimally without compromising the other.
2Reliability
If cell pitch is reduced to increase unit cell density, then ON resistance decreases, but manufacturing precision requirements increase
Solution Approach 1:
The device is segmented into first regions and second regions with different base region configurations. This segmentation allows the manufacturing process to use different trench formation conditions for different regions, reducing the overall precision requirements. The first regions can be formed with more relaxed tolerances while the second regions provide the high-density channel structures needed for low ON resistance.
Solution Approach 2:
The invention changes key parameters including the conductivity type and impurity concentration of different base regions. The first p+-type base regions have different properties than the second p+-type base regions, allowing optimization of each region's electrical characteristics. This parameter differentiation enables reduced ON resistance while maintaining manufacturability through relaxed precision requirements in certain regions.
3Ease of manufacture
If conventional trench structure is used, then manufacturing is simpler, but ON resistance is higher and efficiency is lower
Solution Approach 1:
The conventional trench structure is enhanced through segmentation into first and second regions with different base region configurations. This maintains the overall trench fabrication simplicity while introducing localized variations that improve electrical performance. The segmented structure allows standard trench formation processes to be used, followed by selective base region provisioning to achieve low ON resistance and high efficiency.
Solution Approach 2:
The device employs a composite structure combining first p+-type base regions and second p+-type base regions within the trench MOSFET architecture. This composite approach integrates different regional characteristics to achieve both ease of manufacture (through standardized trench processes) and superior electrical performance (through optimized base region configurations that reduce ON resistance and improve power conversion efficiency).
Data Source
AI summary
A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, first base regions of a second conductivity type, second base regions of the second conductivity type, a second semiconductor layer of the second conductivity type, first semiconductor regions of the first conductivity type, second semiconductor regions of the second conductivity type, gate insulating films, gate electrodes, an interlayer insulating film, first electrodes, a second electrode, and trenches. Between adjacent first base regions, at least two of the trenches, at least two of the gate electrodes, and at least two of the second base regions are disposed, the second base regions disposed between the adjacent first base regions being disposed separate from one another and separate from the first base regions, in a direction in which the trenches are arranged.