SiC Trench MOSFET Short Circuit Tolerance via Segmented Drift
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Solution Overview
Problem
Trench gate type MOSFETs using silicon carbide face challenges in maintaining short circuit tolerance due to low on-resistance, leading to reduced time before excessive current flows and breakdown occurs, which decreases short circuit tolerance.
Innovation Solution
Incorporating p-type current limiting regions and field alleviation portions in the silicon carbide layer structure, specifically designed to limit the path of on-current and alleviate fields applied to gate insulating layers, enhancing short circuit tolerance and breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the on-resistance of the MOSFET is reduced to improve conductivity, then the power loss is decreased, but the short circuit tolerance is reduced because excessive current flows more quickly
Solution Approach 1:
The patent divides the drift region into multiple segments with different doping concentrations (first drift region with lower concentration, second drift region with higher concentration). This segmentation allows the device to achieve low on-resistance through the first drift region while the second drift region provides current limiting during short circuits, thus resolving the contradiction between power loss reduction and short circuit tolerance.
Solution Approach 2:
The patent applies local quality by creating regions with different electrical properties within the drift region. The first drift region has lower doping concentration for low resistance, while the second drift region has higher doping concentration for current limiting. This local differentiation allows simultaneous optimization of both power efficiency and short circuit protection.
2Loss of energy
If the current path is shortened to reduce on-resistance, then the conductivity is improved, but the heat generation during short circuit increases
Solution Approach 1:
The drift region is segmented into two parts with different doping concentrations. The first drift region provides a short current path for low on-resistance and reduced heat generation during normal operation, while the second drift region activates during short circuits to limit current and reduce excessive heat generation, thus resolving the contradiction between conductivity and heat generation.
Solution Approach 2:
The patent changes the doping concentration parameter along the current path. The first drift region has lower doping concentration for low resistance, while the second drift region has higher doping concentration to limit current during short circuits. This parameter change allows the device to maintain low heat generation during normal operation while preventing excessive heat during short circuits.
3Loss of energy
If the trench gate structure is used to reduce on-resistance, then the device efficiency is improved, but the field strength at the gate insulating layer increases leading to breakdown
Solution Approach 1:
The patent applies local quality by creating a field alleviation portion with different doping characteristics at the location where the gate insulating layer contacts the drift region. This local modification reduces the electric field strength at the critical interface, preventing breakdown while maintaining the efficient trench gate structure for low on-resistance and high device efficiency.
Solution Approach 2:
The field alleviation portion is designed to preemptively counteract the high electric field that would otherwise cause breakdown at the gate insulating layer interface. By introducing this region with appropriate doping concentration before the breakdown occurs, the patent prevents the harmful effect while maintaining the benefits of the trench gate structure.
Data Source
AI summary
A semiconductor device according to an embodiment includes a silicon carbide layer having a first plane and a second plane; a source electrode; a drain electrode; first and second gate electrodes located; an n-type drift region and a p-type body region; n-type first and second source regions; a p-type first silicon carbide region and p-type second silicon carbide region having a p-type impurity concentration higher than the body region; first and second gate insulating layers; a p-type third silicon carbide region contacting the first silicon carbide region, a first n-type portion being located between the first gate insulating layer and the third silicon carbide region; and a p-type fourth silicon carbide region contacting the second silicon carbide region, a second n-type portion being located between the second gate insulating layer and the fourth silicon carbide region.