SiC MOSFET Contact Layout for Bipolar Degradation Control
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Solution Overview
Problem
Conventional silicon carbide semiconductor devices experience bipolar degradation due to basal plane dislocations growing into stacking faults during body diode conduction, leading to increased on-voltage and conduction loss.
Innovation Solution
A silicon carbide semiconductor device with a uniform layout of p++-type contact regions and contact holes across the active region, suppressing variations in resistance and current density, thereby inhibiting stacking fault growth and reducing bipolar degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If p++-type contact regions are scattered in island-like shapes with larger surface area near the center of the active region, then current density distribution improves, but stacking fault growth is promoted leading to bipolar degradation
Solution Approach 1:
The patent applies local quality by varying the surface area of p++-type contact regions based on their position in the active region. Contact regions near the center have smaller surface areas compared to those near the periphery, creating a non-uniform distribution that compensates for the natural tendency of current to concentrate at the center. This local adjustment prevents excessive current density at the center while maintaining adequate current distribution throughout the active region, thereby suppressing stacking fault growth without sacrificing overall current density uniformity.
2Use of energy by moving object
If body diode conduction occurs during deadtime, then energy regeneration is achieved, but bipolar degradation increases due to stacking fault growth
Solution Approach 1:
The patent converts the harmful effect of body diode conduction (which causes stacking fault growth and bipolar degradation) into a beneficial operation by carefully controlling the layout of p++-type contact regions. By optimizing the contact region geometry and distribution, the patent enables safe body diode conduction during deadtime for energy regeneration while suppressing the harmful stacking fault growth through appropriate current density management. This allows the body diode to perform its useful function without causing the detrimental effects that would otherwise occur.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The uniform layout of p++-type contact regions and contact holes effectively suppresses bipolar degradation by maintaining stable current density and resistance, delaying stacking fault growth even at higher current densities compared to conventional structures.
Implementation Method 1
suppressing variations in resistance and current density
Implementation Method 2
The body diode of the MOSFET is a parasitic p-intrinsic-n (pin) diode formed by a pn junction (main junction) between a p++-type contact region, a p-type base region, an n−-type drift region, and an n+-type drain region
Data Source
AI summary
A p++-type outer peripheral contact region is provided in an edge termination region and surrounds a periphery of an active region in a rectangular shape having rounded corners, in a plan view. The p++-type outer peripheral contact region faces a gate runner on a front surface of a semiconductor substrate via an insulating layer. In the active region, a p++-type region is provided facing a gate pad on the front surface of the semiconductor substrate via the insulating layer. The p++-type outer peripheral contact region and the p++-type region are provided apart from p++-type contact regions that form source contacts with a source electrode. The p++-type contact regions and contact holes in which the source contacts are formed are disposed in a uniform layout spanning an entire area of the active region so that an end side and a center side of the active region have the same layout.