SiC MPS Diode Silicide Thickness Control for Leakage Reduction

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Solution Overview

Problem

Merged PIN Schottky diodes (MPS) using silicon carbide (SiC) face challenges with the silicide layer causing degradation, such as increased leakage current, due to the silicide layer's impact on the anode electrode's ohmic contact and the difficulty in scaling down the device without increasing leakage current.

Innovation Solution

The semiconductor device design includes a specific structure with a p-type SiC substrate, an n-type SiC layer, and silicide layers, where the distance between the SiC substrate and the silicide layer is carefully controlled to be within 0.2 μm or less, and an insulating film is optionally added between the silicide layer and the SiC region to prevent protrusions and reduce leakage current, allowing for self-aligned formation of p-type anode regions and silicide layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a silicide layer is provided between the p-type layer and anode electrode to achieve ohmic contact, then the anode electrode can make ohmic contact with the p-type layer, but leakage current increases due to degradation of characteristics

Engineering Contradiction:
Improveohmic contact qualityVSAvoidleakage current
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent changes the critical parameter of the silicide layer thickness to resolve the contradiction. By controlling the silicide layer thickness to be 0.01 μm or less, the patent achieves both ohmic contact quality and low leakage current. This parameter optimization allows the silicide layer to facilitate ohmic contact while minimizing its harmful effect of increasing leakage current through excessive thickness.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If the device size is scaled down to improve integration, then device density increases, but leakage current increases due to silicide layer issues

Engineering Contradiction:
Improvedevice densityVSAvoidleakage current
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The patent applies parameter changes by precisely controlling the silicide layer thickness to 0.01 μm or less, which enables device scaling down while preventing leakage current increase. This thickness control parameter allows the silicide layer to maintain its beneficial ohmic contact function even in scaled-down devices, thereby supporting higher device density without the penalty of increased leakage current.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If the silicide layer is made thicker to ensure ohmic contact, then contact quality improves, but leakage current increases due to silicide layer degradation

Engineering Contradiction:
Improvecontact qualityVSAvoidleakage current
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent resolves this contradiction by identifying and optimizing the silicide layer thickness parameter. Through precise control to 0.01 μm or less, the patent determines the optimal thickness that provides sufficient ohmic contact quality while preventing the threshold beyond which leakage current begins to increase. This parameter optimization balances contact quality and leakage current suppression.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9748342B2Semiconductor device and method for manufacturing the same
Publication Date: 2017.08.29 KK TOSHIBA
  • US9748342B2 patent drawing
  • US9748342B2 patent drawing
  • US9748342B2 patent drawing

AI summary

A semiconductor device according to an embodiment includes a first-conductivity-type SiC substrate, a first-conductivity-type SiC layer provided on the SiC substrate, having a first surface, and having a lower first-conductivity-type impurity concentration than the SiC substrate, first second-conductivity-type SiC regions provided in the first surface of the SiC layer, second second-conductivity-type SiC regions provided in the first SiC regions and having a higher second-conductivity-type impurity concentration than the first SiC region, silicide layers provided on the second SiC regions and having a second surface, a difference between a distance from the SiC substrate to the second surface and a distance from the SiC substrate to the first surface being equal to or less than 0.2 μm, a first electrode provided to contact with the SiC layer and the silicide layers, and a second electrode provided to contact with the SiC substrate.