SiC Peripheral Step Structure for Stable Breakdown Voltage
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Solution Overview
Problem
Conventional silicon carbide semiconductor devices experience a decrease in breakdown voltage due to suboptimal impurity concentrations and positions of outer peripheral regions, leading to increased electric field concentrations and reduced avalanche breakdown capability.
Innovation Solution
The silicon carbide semiconductor device incorporates a p-type outer peripheral region with optimized impurity concentrations and stepped structures at the outer end, where the impurity concentration of the third outer peripheral region is lower than the upper portions of the p+-type regions, and the steps are arranged in ascending order of proximity to the chip center, mitigating electric field concentrations and enhancing breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the impurity concentration of outer peripheral regions is increased to enhance voltage withstanding capability, then the breakdown voltage improves, but electric field concentration increases leading to reduced avalanche breakdown capability
Solution Approach 1:
The patent applies local quality by creating distinct impurity concentration zones within the outer peripheral region. Specifically, it introduces a first outer peripheral region with a first impurity concentration and a second outer peripheral region with a second impurity concentration that is lower than the first. This spatial variation in impurity concentration allows different sub-regions to serve different functions: the inner region provides voltage withstanding capability while the outer region reduces electric field concentration, thereby resolving the contradiction between these two requirements.
Solution Approach 2:
The patent employs parameter changes by systematically varying the impurity concentration parameter across different regions. The impurity concentration is optimized to be higher in the first outer peripheral region compared to the second outer peripheral region. This parameter optimization allows the device to achieve both high breakdown voltage (through the higher concentration region) and reduced electric field concentration (through the lower concentration region), thus resolving the technical contradiction.
2Device complexity
If the outer peripheral region structure is simplified to reduce manufacturing complexity, then device complexity decreases, but breakdown voltage stability deteriorates
Solution Approach 1:
The patent applies segmentation by dividing the outer peripheral region into multiple distinct zones: a first outer peripheral region with a first impurity concentration and a second outer peripheral region with a second impurity concentration. This segmentation allows each sub-region to be optimized for specific functions, ensuring breakdown voltage stability while maintaining a manageable manufacturing process through systematic regional differentiation rather than complex multi-layer structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses electric field concentrations and maintains a stable breakdown voltage, ensuring the device's reliability and performance comparable to the active region's design value, even under avalanche conditions.
Implementation Method 1
mitigating electric field concentrations and enhancing breakdown voltage
Implementation Method 2
ensuring the device's reliability and performance comparable to the active region's design value, even under avalanche conditions
Data Source
AI summary
A semiconductor device having, in an outer peripheral portion of an active region, and in a depth direction from a front surface of a semiconductor substrate, first to fourth outer peripheral regions, to thereby form steps that are recessed stepwise toward the center of the semiconductor device by a same width, and are arranged in an ascending order of the proximity to the center in the depth direction. The first, second, and fourth outer peripheral regions, respectively, are formed concurrently with p++-type contact regions, a p-type base region, and lower portions of p+-type regions in a center portion of the active region. An impurity concentration of the third outer peripheral region is 0.1 times to 0.5 times the impurity concentration of the upper portions of the p+-type regions. A voltage withstanding structure is formed in contact with an outer end of the first outer peripheral region.