SiC Planar Gate Structure for Current Sensing ESD
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Solution Overview
Problem
Conventional semiconductor devices with silicon carbide (SiC) have a small sensing effective region, leading to low gate capacitance and electrostatic discharge (ESD) capability for the current sensing portion, which is inadequate compared to the main semiconductor element, and the trench gate structure's precision issues result in degraded device characteristics and reduced yield.
Innovation Solution
The semiconductor device incorporates a planar gate structure in the non-operating region, extending gate insulating films and gate electrodes on the semiconductor substrate's surface, increasing gate capacitance and ESD capability, and forms a pn junction to sustain a predetermined breakdown voltage, avoiding dielectric breakdown and precision-related issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a trench gate structure is used in the current sensing portion, then the device can be manufactured with standard processes, but the sensing effective region becomes small resulting in low gate capacitance and ESD capability
Solution Approach 1:
The patent inverts the conventional approach by using a planar gate structure instead of a trench gate structure in the current sensing portion. This inversion allows the gate insulating film and gate electrode to extend over a larger area including the non-operating region, thereby increasing gate capacitance and ESD capability while maintaining manufacturability through standard semiconductor processing techniques.
Solution Approach 2:
The planar gate structure serves multiple functions: it provides the necessary gate control for the current sensing portion, increases gate capacitance for better ESD protection, and utilizes the non-operating region effectively. The gate insulating film and gate electrode extend into areas that would otherwise be unused, making the structure multi-functional and improving overall device reliability.
2Ease of manufacture
If a trench gate structure is used, then the device can be manufactured, but precision issues arise resulting in degraded device characteristics and reduced yield
Solution Approach 1:
The patent replaces the trench gate structure with a planar gate structure, inverting the conventional design approach. This eliminates the precision-related problems associated with trench formation while maintaining the ability to manufacture the device using standard semiconductor processes. The planar structure is inherently more robust to manufacturing variations.
Solution Approach 2:
The planar gate structure uses simpler, more robust materials and fabrication steps that are less sensitive to precision requirements. Instead of requiring precise trench formation and filling, the planar approach uses conventional layer deposition and patterning that are more tolerant of manufacturing variations, thereby improving yield.
3Adaptability or versatility
If the sensing effective region is made small to accommodate other circuit regions, then more circuit functions can be integrated, but gate capacitance and ESD capability are reduced
Solution Approach 1:
The patent extends the gate insulating film and gate electrode into the non-operating region, effectively utilizing the lateral dimension to increase the gate capacitance area. This dimensional extension allows the current sensing portion to achieve sufficient ESD capability without encroaching on the active device regions, thereby maintaining circuit integration density while improving reliability.
Solution Approach 2:
The non-operating region is repurposed to serve as an extended gate region for ESD protection. This multi-functional use of the non-operating region allows it to contribute to both circuit integration and ESD capability, resolving the contradiction between these two requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the ESD capability and gate capacitance of the current sensing portion, maintaining device reliability and stability while avoiding the precision challenges of trench gate structures, thereby improving overall semiconductor device performance.
Implementation Method 1
increasing gate capacitance and ESD capability
Implementation Method 2
forms a pn junction to sustain a predetermined breakdown voltage, avoiding dielectric breakdown
Data Source
AI summary
A semiconductor device having, in a main non-operating region that is free of unit cells of a main semiconductor element, a gate insulating film and a gate electrode of a current sensing portion extending on a front surface of a semiconductor substrate, to thereby form a planar gate structure. A gate capacitance of the planar gate structure is a gate capacitance of the current sensing portion. Directly beneath the planar gate structure, at the front surface of the semiconductor substrate, a structure is provided in which, from a front side of the semiconductor substrate, a p-type region, an n-type region, and a p-type region are stacked, whereby electric field is not applied to the extended portions of the gate insulating film.