SiC RF MOSFET Recessed Gate Structure for Dielectric Breakdown Control
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Solution Overview
Problem
In vertical power transistors like VMOSFETs, the center of the JFET region is a weak point for long-term reliability of the gate dielectric, especially under high-frequency operation and heavy-ion bombardment, leading to potential dielectric breakdown and device damage.
Innovation Solution
A trench filled with an insulating material is formed in the JFET region to protect the gate dielectric, reducing the electric field and capacitance, and the trench can be deep enough to penetrate through the epitaxy layer, with optional sacrificial oxide or nitrogen passivation to improve interface quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a wide gate pitch is used to allow gate metal placement on polysilicon gate for high-frequency operation, then the device can operate at radio frequencies, but the gate-to-drain capacitance and gate-to-source capacitance increase, degrading high-frequency performance
Solution Approach 1:
The gate structure is segmented into multiple fingers with trenches between them, creating isolated gate regions. This segmentation reduces the effective capacitance between gate and drain/source while still allowing adequate metal placement area for RF operation.
Solution Approach 2:
An intermediary dielectric layer is introduced between the gate metal and the semiconductor surface, specifically in the regions between gate fingers. This intermediary structure reduces parasitic capacitance while maintaining the necessary gate control over the channel.
2Ease of operation
If the gate pitch is widened for RF applications, then metal placement is feasible, but the electric field shielding at the JFET region interface deteriorates, increasing dielectric breakdown risk
Solution Approach 1:
A sacrificial oxide layer is formed preliminarily at the interface between the gate dielectric and JFET region before final dielectric deposition. This preliminary action creates a protective barrier that prevents heavy-ion-induced charge from reaching the dielectric interface, thereby preventing breakdown even with wide gate pitch.
Solution Approach 2:
The sacrificial oxide layer acts as a cushioning barrier formed beforehand to absorb or deflect heavy-ion-induced charge, protecting the gate dielectric from breakdown stress before the damaging event occurs.
3Reliability
If a trench is formed in the JFET region to protect the gate dielectric, then dielectric breakdown resistance improves, but the device structure and manufacturing complexity increase
Solution Approach 1:
The trench structure is implemented locally only where needed - between gate fingers and at critical interfaces - rather than throughout the entire device. This localized approach provides necessary protection while minimizing overall structural complexity and manufacturing burden.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the reliability of VMOSFETs by reducing reverse transfer capacitance and electric field stress, allowing for wider gate pitches without degrading high-frequency performance or increasing the risk of dielectric breakdown.
Implementation Method 1
the design of the VMOSFET should provide adequate shielding of the electric field near the interface between the JFET region and the gate dielectric
Implementation Method 2
with optional sacrificial oxide or nitrogen passivation to improve interface quality
Data Source
AI summary
A Field Effect Transistor (FET) may include a semiconductor substrate having a first conductivity type, a semiconductor layer of the first conductivity type formed over the substrate, and a pair of doped bodies of a second conductivity type opposite the first conductivity type formed in the semiconductor layer. A trench filled with a trench dielectric is formed within a region between the doped bodies. The FET may be a Vertical Metal-Oxide-Semiconductor FET (VMOSFET) including a gate dielectric disposed over the region between the doped bodies and the trench, and a gate electrode disposed over the gate dielectric, wherein the trench operates to prevent breakdown of the gate dielectric, or the FET may be a Junction FET. The FET may be designed to operate at radio frequencies or under heavy-ion bombardment. The semiconductor substrate and the semiconductor layer may comprise a wide band-gap semiconductor such as silicon carbide.