SiC Semiconductor Device With Oblique Insulating Surfaces
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high mobility, low on-resistance, and high breakdown voltage while suppressing electric field concentration, which are essential for improving their overall characteristics.
Innovation Solution
The semiconductor device incorporates a silicon carbide member with specific conductivity types and regions, along with strategically positioned electrodes and insulating members, where the surfaces of the insulating regions are oblique to the (0001) plane of the silicon carbide member, thereby controlling the electric field and enhancing device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor device structures are used, then manufacturing is simpler, but mobility is low and on-resistance is high
Solution Approach 1:
The semiconductor device is divided into multiple distinct regions including a first region with first conductivity type, a second region with second conductivity type, and a third region with third conductivity type. Each region serves specific functional purposes to optimize overall device performance while managing complexity through functional segmentation
Solution Approach 2:
Different regions of the semiconductor device are assigned different conductivity types and doping concentrations tailored to local functional requirements. The first region has first doping concentration, the second region has second doping concentration, and the third region has third doping concentration, allowing each area to be optimized for its specific role in charge transport and field control
2Reliability
If higher doping concentrations are used to reduce on-resistance, then on-resistance decreases, but breakdown voltage decreases
Solution Approach 1:
The patent implements spatially varying doping concentrations across different regions. The first region has first doping concentration optimized for low on-resistance, the second region has second doping concentration for field control, and the third region has third doping concentration for breakdown voltage enhancement. This local optimization allows simultaneous achievement of low on-resistance and high breakdown voltage
Solution Approach 2:
The semiconductor device employs asymmetric doping concentration distribution and asymmetric conductivity type arrangement. The doping concentrations follow a specific asymmetric pattern where first doping concentration, second doping concentration, and third doping concentration are deliberately different to create non-uniform electric field distribution that benefits both low on-resistance and high breakdown voltage
3Reliability
If electric field concentration is not suppressed, then device structure is simpler, but reliability is reduced due to high electric field concentration
Solution Approach 1:
The patent employs local quality optimization by assigning specific conductivity types and doping concentrations to different regions. The second region with second conductivity type and second doping concentration is specifically configured to control and distribute the electric field, preventing concentration at critical interfaces while maintaining overall device reliability
Solution Approach 2:
The second region acts as an intermediary between the first region and the third region, mediating the electric field distribution. This intermediate region with its specific conductivity type and doping concentration serves to smooth out electric field transitions and prevent sharp field concentration that would compromise device reliability
Data Source
AI summary
According to one embodiment, a semiconductor device includes a silicon carbide member, first, second, and third electrodes, and a first insulating member. The silicon carbide member includes first, second, and third silicon carbide regions. The first silicon carbide region includes first, second, third, and fourth partial regions. The third partial region is between the first and second partial regions. The fourth partial region is between the third partial region and the first electrode. The second silicon carbide region includes first and second semiconductor regions. The third silicon carbide region includes third and fourth semiconductor regions. The first insulating member includes first, second, and third insulating regions. The second electrode is electrically connected to the first silicon carbide region. The third and fourth partial regions are between the second and first electrodes. The third electrode is electrically connected to the second silicon carbide region.