SiC Semiconductor Device with Parallel Circuit Units
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Solution Overview
Problem
Power semiconductor devices face issues with device breakdown due to overshoot voltage during switching operations, which is exacerbated by high parasitic inductance, leading to increased switching loss and reduced switching speed.
Innovation Solution
The semiconductor device is designed with multiple circuit units in parallel, each equipped with SiC MOSFETs and capacitors to reduce parasitic inductance, and optionally includes magnetic shielding to minimize mutual inductance, allowing for faster switching and reduced switching loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the switching period is made longer to suppress overshoot voltage, then device breakdown due to overshoot is reduced, but switching operation becomes slower and switching loss increases
Solution Approach 1:
The patent changes the electrical parameters of the system by reducing parasitic inductance through optimized circuit layout and connection structures. This allows the switching period to be kept short (maintaining high switching speed) while still suppressing overshoot voltage (maintaining device reliability), thus resolving the contradiction between switching speed and overshoot suppression.
2Object-affected harmful factors
If the switching period is made longer to reduce switching frequency, then overshoot voltage is suppressed, but switching loss increases
Solution Approach 1:
By reducing parasitic inductance through optimized circuit design, the patent enables the system to operate at higher switching frequencies without experiencing excessive overshoot voltage. This results in lower switching loss (since switching loss is proportional to switching frequency when overshoot is controlled) while maintaining overshoot suppression, thus resolving the contradiction between overshoot suppression and energy loss.
3Productivity
If parasitic inductance is reduced to suppress overshoot and reduce switching loss, then switching performance improves, but device complexity increases
Solution Approach 1:
The patent divides the power semiconductor module into multiple independent circuit units, each with its own switching elements and capacitors. This segmentation allows for reduced parasitic inductance in each unit while keeping the overall module structure modular and manageable, thus improving switching performance without excessive complexity increase.
Solution Approach 2:
The patent optimizes the spatial arrangement of circuit elements in three-dimensional space, using vertical stacking and optimized trace routing to reduce parasitic inductance. This dimensional optimization allows for low parasitic inductance without significantly increasing the planar footprint or overall complexity of the module structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses overshoot voltage, enhances switching speed, and decreases switching loss by distributing current and inductance across multiple units, while also providing mechanical protection and improved heat release properties.
Implementation Method 1
capacitors to reduce parasitic inductance
Implementation Method 2
optionally includes magnetic shielding to minimize mutual inductance
Data Source
Figure 1
Figure 2A~2B
Figure 3
AI summary
A semiconductor device of an embodiment includes: a substrate; circuit units arranged above the substrate, each of the circuit units including a first electrode, a second electrode, a first switching element and a second switching element electrically connected in series between the first electrode and the second electrode, a capacitor electrically connected in parallel to the first switching element and the second switching element between the first electrode and the second electrode, and an AC electrode connected between the first switching element and the second switching element; and a housing that encloses the circuit units. A common potential is applied to the first electrodes of the respective circuit units, a common potential is applied to the second electrodes of the respective circuit units, and the AC electrodes of the respective circuit units are connected to one another.