SiC Sensor Electrode Layout for Short-Circuit Ruggedness
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Solution Overview
Problem
Existing SiC power semiconductor devices face challenges in improving their short-circuit withstand time and short-circuit current capability.
Innovation Solution
A vertical power semiconductor device is designed with a silicon carbide (SiC) semiconductor body, including a transistor cell area, gate structures, and a sensor electrode. The device incorporates interlayer dielectrics with specific band offsets to manage thermal leakage currents, enabling a fast feedback loop to turn off the device during short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SiC power semiconductor devices are used, then the device structure is simple, but the short-circuit withstand time and short-circuit current capability are insufficient
Solution Approach 1:
The device is segmented into distinct functional regions: a first interlayer dielectric region with low conduction band offset (1-2.5 eV) for thermal leakage current generation, and a second interlayer dielectric region with higher conduction band offset for normal operation. This segmentation allows the sensor electrode to detect thermal leakage currents specifically from the first region, enabling short-circuit detection without affecting normal device operation.
Solution Approach 2:
The sensor electrode acts as an intermediary element that detects thermal leakage currents flowing through the first interlayer dielectric. This intermediary detection mechanism provides a feedback signal that triggers the short-circuit protection function, allowing the device to distinguish between normal operation and short-circuit conditions without directly monitoring the main power current.
2Reliability
If the short-circuit current capability is improved, then the thermal leakage current detection sensitivity increases, but the on-state resistance may be affected
Solution Approach 1:
The first interlayer dielectric is positioned locally between the sensor electrode and the gate electrode or gate interconnection, creating a localized region for thermal leakage current generation. This local quality approach ensures that the low conduction band offset property is confined to a specific area, allowing sensitive thermal leakage detection without introducing energy losses across the entire device structure during normal operation.
Solution Approach 2:
The conduction band offset parameter of the interlayer dielectric is specifically changed in the first region (1-2.5 eV) compared to conventional devices, enabling enhanced thermal leakage current generation at operating temperatures. This parameter change is localized and controlled, allowing the sensor to detect short-circuit conditions through increased thermal leakage current while maintaining normal on-state resistance characteristics in other device regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the short-circuit ruggedness of SiC power semiconductor devices without affecting the on-state resistance, allowing for effective thermal management and rapid shutdown during short circuits.
Implementation Method 1
A value of a conduction band offset at a first interface of the first interlayer dielectric to the sensor electrode may range from 1 eV to 2.5 eV
Data Source
AI summary
A vertical power semiconductor device includes a silicon carbide (SiC) semiconductor body having opposite first and second surfaces. The SiC semiconductor body includes a transistor cell area including gate structures, a gate pad area, and an interconnection area electrically coupling a gate electrode of the gate structures and a gate pad of the gate pad area via a gate interconnection. The vertical power semiconductor device further includes a sensor electrode and a first interlayer dielectric having a first interface to the sensor electrode and a second interface to at least one of the gate electrode or the gate interconnection. A conduction band offset at the first interface ranges from 1 eV to 2.5 eV. The vertical power semiconductor device further includes a second interface to at least one of the gate electrode or the gate interconnection. The second interlayer dielectric laterally adjoins to the first interlayer dielectric.